way to compare behavioral to structural model? 
Author Message
 way to compare behavioral to structural model?

Hi,
I was wondering how all of you do comparisons of your behavi{*filter*}model
to your structural(netlisted) verilog simulation.  Our chips are getting
much larger and for me to manually look over all the waveforms would be
a real pain.  So what I would need to do is create a high level
behavi{*filter*}model that states how the circuit performs.  Then I would
netlist my schematic and get a "structural" verilog netlist.  I would
then feed these two netlists my input stimulus, and compare the output.
If the structual netlist output matches my intended (behavioral) model,
then I am ok.  If it does not match, I would like to know how many "bit
errors" (number of mismatches) I have.

Any ideas?
--
------------------------------------------------------------------------
Karl Fritz
Design  Engineer                                voice: 507.284.0062

Special Purpose Processor Development Group - Mayo Foundation
------------------------------------------------------------------------



Mon, 22 Oct 2001 03:00:00 GMT  
 way to compare behavioral to structural model?
To expand on this a little more, I see what you are saying in that if my
behavi{*filter*}description matches my netlist, I should be good to go, but I
guess I was not as clear in my goal as I should have been.  What I would
like to do is basically find out the max operating speed where no
"bit-errors" occur.  So what I would have is a behavi{*filter*}model that
says what the circuit does (with no delay information, just
functionality).  Then my structural model would contain the delays and
such so that I could run the structural model faster and faster, and be
able to compare the result to the behavi{*filter*} circuit telling me if I am
losing bits or not.  Would the tool you mentioned be able to accomplish
this?  Maybe this could be done in some way using PLI?  Maybe there is a
program already written for this using PLI?

thanks



 > Hi,
 > I was wondering how all of you do comparisons of your behavi{*filter*}
model
 > to your structural(netlisted) verilog simulation.  Our chips are
getting
 > much larger and for me to manually look over all the waveforms would
be
 > behavi{*filter*}model that states how the circuit performs.  Then I would
 > netlist my schematic and get a "structural" verilog netlist.  I would
 > then feed these two netlists my input stimulus, and compare the
output.
 > If the structual netlist output matches my intended (behavioral)
model,
 > then I am ok.  If it does not match, I would like to know how many
"bit
 > errors" (number of mismatches) I have.
 >
 > Any ideas?

Quote:

>    Hello Karl,

>    There are two ways of doing this:

>    First, as you said, you can create a top level module
>    which instantiates a behavi{*filter*}model (say, u1) and the
>    actual design in gates (say, u2) and then compare the
>    outputs of u1 and u2.

>    However, the present trend seems to be little different.
>    The buzzword for this is "Formal Verification". There are a
>    number of companies who sell tools for this. In the past, I
>    have used Chrysalis' formal verification tool for this
>    (comparing RTL and gates) in the past. When the process
>    is not very straight forward for a first timer (you will
>    have to create a number of attribute files), but, at the end,
>    it worked more or less (apart from the unrelated issues -
>    depending on the size of your design, it may hog all the
>    memories and sometime may run out of it.)

>    On the brighter side, Formal Verification does not need input
>    vectors - it employs a graph comparison method to compare the
>    design trees and finds out any mismatch. So, if your two designs
>    are declared to be equivalent by a formal verification tool,
>    they are equivalent for *all test vectors*.

>    Good luck.
>    - Swapnajit.

--
------------------------------------------------------------------------
Karl Fritz
Design  Engineer                                voice: 507.284.0062

Special Purpose Processor Development Group - Mayo Foundation
------------------------------------------------------------------------


Mon, 22 Oct 2001 03:00:00 GMT  
 way to compare behavioral to structural model?
Hi,

        Generally, I have an other approach. I design a test bench
wich test the functionnality of all functions of the circuits (the
test bench stop or go out or write a log file when expected outputs
doesn'nt match simulated one).
        Ideally, I try to make this the closer as possible to the specification
of the function.
        In fact the verilog test bench is a sort of automatic waveform
verification that you have speak about before.

        I apply this testbench on behavi{*filter*}and structural (before
and after place and route, in min. typ. max, with and without derating
factors).
        I also try to use the same testbench to generate test patterns.
Generally, it consists of the less possible modifications to the
testbench to reduce pat. numbers and run it on structural on all
the above conditions.

        I am not sure it is the best way (is exist a perfect way ?)
but like for all others way, it has his advantage and disadvantages :

        - It is a labor way : From all my past experience, i have seen
that there are around 5 to 10 test bench code lines for 1 behavi{*filter*}
code line !

        - It imposes very strict and self-constraints testbench design, that
should give the higher coverage possible. Sounds difficult
sometimes to be close to this healthy way when time to market pressure
is high.

        - Neverthless, if you design carefully the test bench, I find
this way secure because you test what is specified, no more no less.
I have never had "bad circuits" in the sense that I have never seen
a silicon behavior different from my test bench simulation results
(In fact for my first steps of silicon qualification, i physically run
the main simulation tests).

        - Test pattern generation is naturally in the design flow.
Moreover, you should respect fault coverage limits (90%) before
launching circuit in fab. Having test pattern test bench close to
functionnal test bench helps to know uncovered circuits points which
are too uncovered functionnal behavior.

        Comments greatly welcomed ! In a time when we are currently
investigating in verification and design help tools ...


Quote:

> Hi,
> I was wondering how all of you do comparisons of your behavi{*filter*}model
> to your structural(netlisted) verilog simulation.  Our chips are getting
> much larger and for me to manually look over all the waveforms would be
> a real pain.  So what I would need to do is create a high level
> behavi{*filter*}model that states how the circuit performs.  Then I would
> netlist my schematic and get a "structural" verilog netlist.  I would
> then feed these two netlists my input stimulus, and compare the output.
> If the structual netlist output matches my intended (behavioral) model,
> then I am ok.  If it does not match, I would like to know how many "bit
> errors" (number of mismatches) I have.

> Any ideas?
> --
> ------------------------------------------------------------------------
> Karl Fritz
> Design  Engineer                                voice: 507.284.0062

> Special Purpose Processor Development Group - Mayo Foundation
> ------------------------------------------------------------------------



Tue, 23 Oct 2001 03:00:00 GMT  
 way to compare behavioral to structural model?
Karl,
I think you just discovered why formal verification is needed.
You have several formal verification tools in the market that may do your
job.
Am other suggestion would be to  consider a product like CompareScan of
(former) DesignAcceleration (now Cadence), but this tool is cycle oriented.
Hope it helps,
  Andi Carmon

Quote:

>Hi,
>I was wondering how all of you do comparisons of your behavi{*filter*}model
>to your structural(netlisted) verilog simulation.  Our chips are getting
>much larger and for me to manually look over all the waveforms would be
>a real pain.  So what I would need to do is create a high level
>behavi{*filter*}model that states how the circuit performs.  Then I would
>netlist my schematic and get a "structural" verilog netlist.  I would
>then feed these two netlists my input stimulus, and compare the output.
>If the structual netlist output matches my intended (behavioral) model,
>then I am ok.  If it does not match, I would like to know how many "bit
>errors" (number of mismatches) I have.

>Any ideas?
>--
>------------------------------------------------------------------------
>Karl Fritz
>Design  Engineer voice: 507.284.0062

>Special Purpose Processor Development Group - Mayo Foundation
>------------------------------------------------------------------------



Thu, 25 Oct 2001 03:00:00 GMT  
 
 [ 6 post ] 

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