Synthesis of wait statements 
Author Message
 Synthesis of wait statements

Hi,

I have a VHDL design with sensitivity lists in different
processes and it simulates perfectly.

The design is synthesized using SYNOPSYS and simulate it and
it does n't work at all. My guess was that it did not relate
to the sensitivity lists correctly. So, I looked in the
online manuals and found an example where they replace

Quote:
> process (signalx)
> begin

with

Quote:
> process
> begin
>   wait until signalx'event;

Now, when I do that replacement the VHDL simulation is still
running perfectly.
But, when I try to synthesize it, SYNOPSYS design_analyzer
complains that

Quote:
> Error: This form of wait statement is not supported for
> synthesis on line 80 (VHDL-2150).

Again, I digged up this error in the online manuals but
there was not any more information.

Does anybody has an idea about how to go about this problem?

Thanks,
--

VLSI Research Group, E&CE Department, University of Waterloo
Phone: (519) 888-4567 ext 5035          Home: (519) 886-2790
Fax: (519) 746-5195                         Office: DC 3577A



Tue, 28 Dec 1999 03:00:00 GMT  
 Synthesis of wait statements

Quote:

> Hi,

> I have a VHDL design with sensitivity lists in different
> processes and it simulates perfectly.

> The design is synthesized using SYNOPSYS and simulate it and
> it does n't work at all. My guess was that it did not relate
> to the sensitivity lists correctly. So, I looked in the
> online manuals and found an example where they replace

> > process (signalx)
> > begin

> with

> > process
> > begin
> >   wait until signalx'event;

> Now, when I do that replacement the VHDL simulation is still
> running perfectly.
> But, when I try to synthesize it, SYNOPSYS design_analyzer
> complains that

> > Error: This form of wait statement is not supported for
> > synthesis on line 80 (VHDL-2150).

> Thanks,
> --

> VLSI Research Group, E&CE Department, University of Waterloo
> Phone: (519) 888-4567 ext 5035          Home: (519) 886-2790
> Fax: (519) 746-5195                         Office: DC 3577A

Hi,

I am not clear about what your original problem is, but I believe I do
understand why you get the compiler-error when you try to synthesize the
wait statement.

For synthesis purposes, the Synopsys compiler infers a flipflop
triggered off the rising-edge of signalx from the following description.

   process
   begin
     wait until signalx'event and signalx = '1';

(If you replace the '1' by a '0', you get a flipflop triggered off the
falling-edge of signalx.)

In your code, you specify an event on signalx, but do not specify a
rising edge or a falling edge. The compiler interprets the signalx'event
as implying a flipflop, but then fails to compile, since the edge is not
specified.

The basic problem is that the synthesis compiler works on a different
set of assumptions, and uses a subset of the IEEE standard VHDL.

Here are some basic guidelines/examples for synthesis:
  1. try defining combinational and sequential logic in separate
     processes.
  2. If you have a process which describes purely combinatorial logic,
     use a fully specified sensitivity list, but DO NOT USE any wait
     statements or 'event keywords.
  3. If you want to synthesize an edge triggered flipflop, use either of
     the following styles:

       process(signalx)
       begin
         wait until signalx'event and signalx = '1';
              q <= d;
       end process;

                       OR
       process(signalx)
       begin
         if signalx'event and signalx = '1' then
              q <= d;
         end if;
       end process;

  4. If you need a level triggered latch,

       process(signalx)
       begin
         if signalx = '1';
              q <= d;
       end process;

It is debatable whether Synopsys Design Compiler is interpreting the
'event keyword in the correct sense. But as long as you stick to the
coding style they reccommend, I have found that you get very reliable
synthesis results.
If you are doing synthesis, it would be a good idea to go through the
design compiler methodology in the online documentation first.

Hope that helps,

Hari Krishnan,
MTS, Visual Systems,
Silicon Graphics, Inc.




Fri, 31 Dec 1999 03:00:00 GMT  
 Synthesis of wait statements

Quote:

> > process
> > begin
> >   wait until signalx'event;

> Now, when I do that replacement the VHDL simulation is still
> running perfectly.
> But, when I try to synthesize it, SYNOPSYS design_analyzer
> complains that

> > Error: This form of wait statement is not supported for
> > synthesis on line 80 (VHDL-2150).

Hi Amr,

SYNOPSYS (like the most synthesis tools) only support a
WAIT UNTIL "CLOCK EDGE EXPRESSION" statement in a clocked process.

The WAIT UNTIL SIGNAL'EVENT is 4 simulation purposes only.
Therefore if u wait 4 a change of a value use the sensitivity list.

Hope it helps u.
Rgds copi
--
 -----------------------------------------------------------------
| Heiko Copius,  MSS / EI          | Tel.: +49 (0)3677 69 1172    |
| Technical University of Ilmenau  |                   or 1168    |
| PF 10565, 98684 Ilmenau, Germany | FAX : +49 (0)3677 69 1163    |
|-----------------------------------------------------------------|

| WWW   : http://www.inf-technik.tu-ilmenau.de/~copi              |
 -----------------------------------------------------------------



Sat, 01 Jan 2000 03:00:00 GMT  
 Synthesis of wait statements

Hi Amr,
try to do wait until rising_edge(signalx) instead.
At least tell the synthesis tool which edge you runs on
(check the event, last_value ... attributes)

If you go for a event you need something that trigger on both
edges, right ........

/Kenneth



Quote:

> Hi,

> I have a VHDL design with sensitivity lists in different
> processes and it simulates perfectly.

> The design is synthesized using SYNOPSYS and simulate it and
> it does n't work at all. My guess was that it did not relate
> to the sensitivity lists correctly. So, I looked in the
> online manuals and found an example where they replace

> > process (signalx)
> > begin

> with

> > process
> > begin
> >   wait until signalx'event;

> Now, when I do that replacement the VHDL simulation is still
> running perfectly.
> But, when I try to synthesize it, SYNOPSYS design_analyzer
> complains that

> > Error: This form of wait statement is not supported for
> > synthesis on line 80 (VHDL-2150).

> Again, I digged up this error in the online manuals but
> there was not any more information.

> Does anybody has an idea about how to go about this problem?

> Thanks,
> --

> VLSI Research Group, E&CE Department, University of Waterloo
> Phone: (519) 888-4567 ext 5035          Home: (519) 886-2790
> Fax: (519) 746-5195                            Office: DC 3577A



Sat, 01 Jan 2000 03:00:00 GMT  
 Synthesis of wait statements

Quote:

>   4. If you need a level triggered latch,

>        process(signalx)
>        begin
>          if signalx = '1';
>               q <= d;
>        end process;

A minor correction, this process does not describe a level sensitive
latch.  It is another description for a positive-edge triggered flop,
since the only time that "q" gets re-evaluated is when "signalx" changes
and "signalx = '1'".  In order to make it a level sensitive latch, the
code would need to be:

   process( signalx, d )
   begin
      if signalx = '1' then q <= d;
   end process ;

Darren Lasko
Fusion MicroMedia Corporation



Sun, 02 Jan 2000 03:00:00 GMT  
 Synthesis of wait statements

: Hi,

: I have a VHDL design with sensitivity lists in different
: processes and it simulates perfectly.

: The design is synthesized using SYNOPSYS and simulate it and
: it does n't work at all. My guess was that it did not relate
: to the sensitivity lists correctly. So, I looked in the
: online manuals and found an example where they replace

: > process (signalx)
: > begin

: with

: > process
: > begin
: >   wait until signalx'event;

: Now, when I do that replacement the VHDL simulation is still
: running perfectly.
: But, when I try to synthesize it, SYNOPSYS design_analyzer
: complains that

: > Error: This form of wait statement is not supported for
: > synthesis on line 80 (VHDL-2150).

: Again, I digged up this error in the online manuals but
: there was not any more information.

: Does anybody has an idea about how to go about this problem?

: Thanks,
: --

: VLSI Research Group, E&CE Department, University of Waterloo
: Phone: (519) 888-4567 ext 5035          Home: (519) 886-2790
: Fax: (519) 746-5195                       Office: DC 3577A

Hi;
You may think at the gate level when you want to perform a synthesis
(RTL level) instead of at comportemental level. Synthesis in VHDL must
be seen as a restriction of VHDL capabilities
Best regards;

--
Patrice Kadionik.
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Tue, 04 Jan 2000 03:00:00 GMT  
 Synthesis of wait statements

I believe in VHDL, to use the wait statement in a synthesizable code, you
need to specify which edge of the signal to continue. You do not need a
sensitivity list when you use a wait statement.

e.g

process
begin
 wait until signalx'event and signalx='1' (positive edge)
      or
 wait until signalx'event and signalx='0' (negative edge)

To double check what your synthesizer accepts you should read up the
manual on synthesizable VHDL code.

Quote:


> > > process
> > > begin
> > >   wait until signalx'event;

> > Now, when I do that replacement the VHDL simulation is still
> > running perfectly.
> > But, when I try to synthesize it, SYNOPSYS design_analyzer
> > complains that

> > > Error: This form of wait statement is not supported for
> > > synthesis on line 80 (VHDL-2150).

> Hi Amr,

> SYNOPSYS (like the most synthesis tools) only support a
> WAIT UNTIL "CLOCK EDGE EXPRESSION" statement in a clocked process.

> The WAIT UNTIL SIGNAL'EVENT is 4 simulation purposes only.
> Therefore if u wait 4 a change of a value use the sensitivity list.

> Hope it helps u.
> Rgds copi
> --
>  -----------------------------------------------------------------
> | Heiko Copius,  MSS / EI          | Tel.: +49 (0)3677 69 1172    |
> | Technical University of Ilmenau  |                   or 1168    |
> | PF 10565, 98684 Ilmenau, Germany | FAX : +49 (0)3677 69 1163    |
> |-----------------------------------------------------------------|

> | WWW   : http://www.inf-technik.tu-ilmenau.de/~copi              |
>  -----------------------------------------------------------------



Tue, 11 Jan 2000 03:00:00 GMT  
 
 [ 7 post ] 

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