VHDL v.s. Verilog : How can I synthesize them? 
Author Message
 VHDL v.s. Verilog : How can I synthesize them?


> ViewLogic's VHDL has basic problems interacting with other VHDL's much
> less Verilog.  Most of this is due to the the way they model bits: they're
> not IEEE 1076 (much less IEEE 1164) compliant and use a creature of their
> own invention called "VL_BIT".  In addition, they don't support type_def's
> so you can't just do a clever rename of "VL_BIT" into something all the
> other VHDL simulators can understand.

>ViewSynthesis 2.4 onwards allows the use of STD_LOGIC.
>This can be used with the new simulator which has the Vantage Kernel.

This is news!  Cool!  Has ViewSynth 2.4 been released yet?  Two - Three months
ago when I did a survey for an article on benchmarking FPGA synthesis tools
no customers mentioned using a 2.4 rev.

At some point I'd like to hear from users or see for myself how ViewLogic
fixed their VHDL non-portability problem with rev 2.4.

                              - John Cooley
                                the ESNUG guy

P.S. Keith, when quoting me could you make sure I'm attributed for the
quote?  (I'm the person who wrote the original observation you were
replying to!)

 Trapped trying to figure out a Synopsys bug?  Want to hear how 3114 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!

     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."

Wed, 23 Apr 1997 01:57:54 GMT  
 [ 1 post ] 

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