Gated Clock(double rate clock)?
Author Message
Gated Clock(double rate clock)?

Hi, all.

I need to make a such pulse according to the clock(clk_60),
for the DVD-RAM write channel.

+--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+
|  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
clk 60MHz   --+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--

+--------+  +--+  +--------+              +--------+  +--+  +--+  +--+
|        |  |  |  |        |              |        |  |  |  |  |  |  |
write pulse --+        +--+  +--+        +--------------+        +--+  +--+  +--+  +--

In my opinion, using double rate clock(clk_120) will be a best solution.
What do you think about that?
So, most of system uses downed clock(clk_60), and write channel uses clk_120.
I should generate two clock trees.
One is used for clk_120, and the other is used for clk_60 which is gated from clk_120.
Is it a good choice? Is it O.K. to generate clock tree from the flipfrop output?
Or is there any another solution?

For example) VHDL case
entity down_clock is
port(
clk_120 : in  std_logic;
reset_n : in  std_logic;
clk_60  : out std_logic
);
architecture code of down_clock is
signal gen_clk : std_logic;
begin
clk_60 <= gen_clk;
p00_clk_gen : process
begin
wait until clk_120'event and clk_120
if (reset_n = '0') then
gen_clk <= '0';
else
gen_clk <= not gen_clock;
end if;
end process;
end code;

-- ***************************************
-- Kyungjin Jang
-- DIT 2R, Daewoo Electronics CO., LTD.
-- ***************************************

Wed, 21 Nov 2001 03:00:00 GMT
Gated Clock(double rate clock)?
Hi,
But usually the overhead of adding a new clk is too big.
Why not to use a negedge FF for this write pulse? It can be much more simple.

Quote:

> Hi, all.

> I need to make a such pulse according to the clock(clk_60),
> for the DVD-RAM write channel.

>               +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+
>               |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |
> clk 60MHz   --+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--+  +--

>               +--------+  +--+  +--------+              +--------+  +--+  +--+  +--+
>               |        |  |  |  |        |              |        |  |  |  |  |  |  |
> write pulse --+        +--+  +--+        +--------------+        +--+  +--+  +--+  +--

> In my opinion, using double rate clock(clk_120) will be a best solution.
> What do you think about that?
> So, most of system uses downed clock(clk_60), and write channel uses clk_120.
> I should generate two clock trees.
> One is used for clk_120, and the other is used for clk_60 which is gated from clk_120.
> Is it a good choice? Is it O.K. to generate clock tree from the flipfrop output?
> Or is there any another solution?

> For example) VHDL case
> entity down_clock is
> port(
>      clk_120 : in  std_logic;
>      reset_n : in  std_logic;
>      clk_60  : out std_logic
> );
> architecture code of down_clock is
>     signal gen_clk : std_logic;
> begin
>     clk_60 <= gen_clk;
>     p00_clk_gen : process
>     begin
>         wait until clk_120'event and clk_120
>         if (reset_n = '0') then
>             gen_clk <= '0';
>         else
>             gen_clk <= not gen_clock;
>         end if;
>     end process;
> end code;

> -- ***************************************
> -- Kyungjin Jang
> -- DIT 2R, Daewoo Electronics CO., LTD.
> -- ***************************************

--

GGGGG
GGGGGGGGG
GGGGGGGGGGGGG
GGGGGGGGGGGGGG
GGGGG
GGGGG          Erez Reches
GGGGG    GGGG  Galileo Technology Ltd.
GGGGG    GGGG  Moshav Manof, D.N. Misgav 20184, ISRAEL

GGGGGGGGGGGG  Tel       -  + 972 4 9999555 ext. 259
GGGGGGGGG   FAX       -  + 972 4 9999574
GGGGG     -----------------------------------------------
check out our web site: http://www.galileoT.com
-----------------------------------------------

Fri, 23 Nov 2001 03:00:00 GMT
Gated Clock(double rate clock)?

Quote:

> Hi,
> But usually the overhead of adding a new clk is too big.
> Why not to use a negedge FF for this write pulse? It can be much more simple.

Thanks.
You are right.
Someone asked me aboubt that question.
But I didn't know the exact soultion.
Your suggestion just fit into it.

-- ***************************************
-- Kyungjin Jang
-- DIT 2R, Daewoo Electronics CO., LTD.
-- ***************************************

Sat, 24 Nov 2001 03:00:00 GMT

 Page 1 of 1 [ 3 post ]

Relevant Pages