San-Jose, CA - ASIC Designers wanted 
Author Message
 San-Jose, CA - ASIC Designers wanted

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"  Double the ASIC performance,
   quadruple functionality,
   hit market on time,
   and don't forget to cut the cost by half while you're at it !..."
              Does this sound like you ?
*************************************************

Silicon-Value is a young startup company that designs and manufactures
ultra-high density full-custom ASiXs for the deep-submicron age.
Compared to traditional cell-based ASICs, Silicon Value's ASiXs can

  * Reduce die area and cost by fifty percent or more
  * Improve performance and power consumption by 2X or more
  * Achieve faster timing closure

We offer an attractive salary and benefits plan with the opportunity
to participate in stock options. So, if you are ready to challenge
yourself with the most advanced technology in the industry, join
Silicon-Value
and know that your designs are making a difference in the VLSI world !

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BACK-END ASIC DESIGNER
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Requirements: Looking for a highly motivated Back-End ASIC design
engineer with expertise in Floorplanning, Place & Route and Physical
Verification.  A BSCS/BSEE degree with 2-4 yrs experience, or
MSCS/MSEE with 1 year of experience (industry or research activity) is
required. Expertise in understanding a netlist representation is
expected. Knowledge of Cadence' Silicon-Ensemble, Design-Planner,
Dracula/Vampire  is a plus. Analog/Mixed-Signal design expertise and
it's integration with the digital portion is a significant plus.

Responsibilities:
   * Work closely with our Front-End team and provide support for
parasitic & wire load extractions
   * Work with our proprietary optimization engine to reduce the
die-size without performance penalty
   * Floorplan and integrate any 3rd party IP blocks
   * P&R the netlist until timing closure is achieved
   * Perform physical verification for sign-off
   * Handle testability related P&R work

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FRONT-END ASIC DESIGNER
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Requirements: Looking for a highly motivated Front-End ASIC design
engineer with expertise in Synthesis (including Test Synthesis),
Functional Verification & Timing Analysis.  A BSCS/BSEE degree with
2-4 yrs experience, or MSCS/MSEE with 1 year of experience (industry
or research) is required. Expertise in HDLs (Verilog & VHDL) is
expected. Knowledge of Synopsys' front-end tools including Design
Compiler, VCC/VCS, Path Mill/Prime Time OR Cadence' NC-Verilog/VHDL,
BuildGates, Pearl is a plus.  Analog/Mixed-Signal design experience
and it's integration with the digital portion is a significant plus.

Responsibilities include:
   * Engage early-on with our customers and understand the HDL
descriptions being developed.  Assist with any 3rd party IP
selections.
   * Synthesize and perform STA on the designs - which requires
floor-planning to generate custom-WLM & parasitics
   * Work on testability aspects (scan-chaining, BIST, Boundary-scan)
and coverage (ATPG, Fault grading)
   * Work with our proprietary optimization engine to reduce the
die-size without performance penalty
   * Work closely with our Back-End team and assist them in the
die-size reduction process

Please forward your resume in electronic format (MS WORD or plain
text) to




Fri, 07 Jun 2002 03:00:00 GMT  
 
 [ 1 post ] 

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