Illegal left-hand-side error. 
Author Message
 Illegal left-hand-side error.

Let me explain my problem with an example.

I want to simulate a circuit on Cadence, with verilog-XL.
For that I need a stimulus file.
Let's say a, b, c, d are the four inputs of my circuit.

Here is what I wrote in my simulus file :

**************************************************

parameter in_width=42, patterns=16, step=50;
integer index;
reg [1:in_width] in_mem[1:patterns];
wire a, b, c, d;

        initial
                begin
                        CK = 0;
                end
        always #25 CK = ~CK;

        initial
                begin
                        $readmemb("../wd.data", in_mem);
                        for (index=1;index<=patterns;index=index+1) #step;
                        if (index == patterns+1) $stop;
                end

        initial
                begin
                        assign {a,b,c,d} = $getpattern(in_mem[index]);
                end

****************************************************

This code should be alright, but at the compilation, I get the following
message :

Error!    Illegal left-hand-side in assign statement      
[Verilog-ILHSFA]    
          "testfixture.new", 23: assign {a,b,c,d} =
getpattern(in_mem[index]);            

Anybody who can explain to me what I wrote wrong, thank you!



Sat, 29 Apr 2000 03:00:00 GMT  
 
 [ 1 post ] 

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