Illegal left-hand-side error. 
Author Message
 Illegal left-hand-side error.

Let me explain my problem with an example.

I want to simulate a circuit on Cadence, with verilog-XL.
For that I need a stimulus file.
Let's say a, b, c, d are the four inputs of my circuit.

Here is what I wrote in my simulus file :


parameter in_width=42, patterns=16, step=50;
integer index;
reg [1:in_width] in_mem[1:patterns];
wire a, b, c, d;

                        CK = 0;
        always #25 CK = ~CK;

                        $readmemb("../", in_mem);
                        for (index=1;index<=patterns;index=index+1) #step;
                        if (index == patterns+1) $stop;

                        assign {a,b,c,d} = $getpattern(in_mem[index]);


This code should be alright, but at the compilation, I get the following
message :

Error!    Illegal left-hand-side in assign statement      
          "", 23: assign {a,b,c,d} =

Anybody who can explain to me what I wrote wrong, thank you!

Sat, 29 Apr 2000 03:00:00 GMT  
 [ 1 post ] 

 Relevant Pages 

1. illegal left-hand side error

2. illegal left-hand-side assignment

3. Bit select adressing on left hand side

4. Concatenation on the Left Hand Side of an Assignment

5. Scale on right-hand side of ?

6. Report cuts off left-hand edge in XP Pro

7. Franz's right vs left hands

8. BUG: Checkbuttons in Windows 98 do not have the left-hand tick

9. Left handed mouse problems

10. Hove to shift page numbers from left to right side depending on even uneven pagenumber

11. Reusing left side of assignments

12. ipadx of a parent with -side left of it's child


Powered by phpBB® Forum Software