Synthesizable Verilog 
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 Synthesizable Verilog

Are there any guidelines available for writing sythesizeable code in
Verilog ?

Bhavin

Sent via Deja.com http://www.*-*-*.com/
Before you buy.



Sun, 02 Mar 2003 03:00:00 GMT  
 Synthesizable Verilog
All synthesis tools come with a description of the subset of Verilog
they support. Also they have synthesis guidelines to describe how to
get certain structures (DFFs with async reset etc) from Verilog
coding. Your best bet is to get the HDL compiler document for Synopsys
Design Compiler because this is the de facto synthesis standard and
almost all other synthesis tool vendors try to follow it.
There is also a standardization effort for Synthesizable subset of
Verilog but it is going to take a while for vendors to support it.
Quote:

>Are there any guidelines available for writing sythesizeable code in
>Verilog ?

>Bhavin

>Sent via Deja.com http://www.deja.com/
>Before you buy.



Mon, 03 Mar 2003 03:00:00 GMT  
 
 [ 2 post ] 

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