Verilog & VHDL co-simulation 
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 Verilog & VHDL co-simulation

Hello all:
I have got a VHDL model and I used it in simulation with verilog
design. Now I am facing a very strange problem.

The VHDL model defined a port which is an INOUT port, named like
VHDL_PORT_A. I connect it to a verilog signal defined in the top level
module, name veri_sig_a. The simulation waveform shows that when the
veri_sig_a is "0", the VHDL_PORT_A can still keep "1". The port
connection is like this:

// verilog shell of that VHDL model
model_a instance_a (
  .VHDL_PORT_A (veri_sig_a),

No warning and no error message reported about this conflict.

I am using the ncverilog simulator. Could anyone gives me an advice or
point out to check where. Thank you very much.


Sun, 13 Nov 2005 18:15:55 GMT  
 [ 1 post ] 

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