One Sheep Farmer's Impressions of SNUG'99 
Author Message
 One Sheep Farmer's Impressions of SNUG'99


   /o o\  /  it's a FEATURE!"                              (508) 429-4357
  (  >  )
   \ - /         "One Sheep Farmer's Impressions Of SNUG'99"
   _] [_        (plus what 23 other engineers saw there, too.)

                              by John Cooley
           Moderator Of The E-mail Synopsys Users Group (ESNUG)

     The 9th Annual Synopsys (& EPIC) Users Group Meeting (SNUG'99)
      at the Doubletree Inn, San Jose, CA, March 29th - 31st, 1999

 First Impressions
 -----------------

   "One thing I liked better about this conference than I did the previous
    time I went was that since Synopsys has a greater range of products,
    the presentations cover a greater range of topics and seem to cover
    almost every aspect of ASIC design."

       - Brad Sonksen of Vixel Corp.

 The Numbers
 -----------

 Because EDA salesdroids and marketeers are known to distort/exaggerate
 what other customers are doing/saying about a particular tool they're
 trying to get you to buy, over the years I've found it necessary to get
 the hard data myself -- whether it be the ratio of Verilog users to VHDL
 users or how many customers attended a specific talk.  This year, the
 numbers controversy was around how many attended Aart's speech.  My
 count at the 30 minute mark was 367.  Immediately after the speech, one of
 the Synopsys people told me: "John, I had two CAE's count the room.  They
 counted 385."  Roughly half an hour after Aart's speech was over, the
 very *same* Synopsys employee told me: "John, I had two CAE's count the
 room.  They counted 470."  I stand by my original 367.

  Monday, March 29                                     Number Of Attendees

    9:00 - 12:15  (MA1) Tutorial on Synthesis Coding Styles    239
    9:00 - 12:15  (MA2) Tutorial of FPGA Compiler II            51
    9:00 - 12:15  (MA4) Tutorial on Behavi{*filter*}Compiler         44
    9:00 - 12:15  (MA5) IP Vendor Reuse Stories & SPINE'99      69

    1:30 - 3:00   (MB1) DC Wire Models & 2 Power Talks    214 + 11 standees
    1:30 - 3:00   (MB2) Eagle, COSSAP, Cyclone, VERA Talks      63
    1:30 - 3:00   (MB3) PrimeTime                         128 +  8 standees

    3:15 - 4:45   (MC1) Make, MIN/MAX Synth, Clk Gating   227 + 17 standees
    3:15 - 4:45   (MC2) BFM Testing, Test Compiler              58
    3:15 - 4:45   (MC3) Large FPGAs, FPGA Express               43

    5:00 - 8:00   Synopsys R&D{*filter*}tail Party                Est. 600

  Tuesday, March 30

    9:00 - 10:15  Keynote Address (Aart's Speech)     367 or (385) or (470)

   10:30 - 11:45  (TA1) Dc_shell, Verilog, VHDL, ECO Compiler  166
   10:30 - 11:45  (TA2) VCS, sim/syn mismatch, LFSRS      128 + 13 standees
   10:30 - 11:45  (TA3) IP Cores, IP w/ PathMill & PrimeTime   101
   10:30 - 11:45  (TA4) EPIC TimeMill, Arcadia, RailMill, ACE   34

    1:30 -  3:00  (TB1) Tcl, Clear Case, FSM_PERL, "Modes"     227
    1:30 -  3:00  (TB2) IP Cores / Design Reuse Talks           96

    3:15 -  4:45  (TC1) Make files, SMART 2.0, RUN_PROJ        161
    3:15 -  4:45  (TC2) Behavi{*filter*}Compiler Experiences         93
    3:15 -  4:45  (TC3) Formality Experiences                   83

    5:00 -  5:45  SNUG'99 Wrap-Up & Best Papers Awards         216

    6:00 -  8:00  Non-Synopsys EDA Vendor Fair Party         over 400

  Wednesday, March 31

    8:00 - 11:15  (WA1) Tutorial of New Stuff in DC 99.05      178
    8:00 - 11:15  (WA2) Tutorial on EPIC PathMill               25
    8:00 - 11:15  (WA3) Tutorial on Design Reuse                61
    8:00 - 11:15  (WA4) Tutorial on Functional Verification     33

    1:00 -  4:00  (WB1) Tutorial on PrimeTime & PathMill        43
    1:00 -  4:00  (WB2) Tutorial on Scan Test w/ DC Expert      31
    1:00 -  4:00  (WB3) Tutorial on TimeMill & PowerMill        11
    1:00 -  4:00  (WB4) Tutorial Module Compiler/BOA/BRT   135 + 7 Standees
    1:00 -  4:00  (WB5) Tutorial on VCS & VERA                  63

 The overall user attendance for SNUG'99 was 528 customers.  Compared to
 the SNUG'98 numbers, 590, this is an 11 percent drop in attendance.  But
 that's no big surprise because SNUG normally 'partners' with OVI/VIUF
 on opposite ends of a particular weekend.  It just so happens that this
 year, that weekend was Easter/Spring Break Weekend -- forcing the two
 conferences to have 5 dead days between them.  As a result, this meant
 that the out-of-towners choose *either* SNUG *or* OVI/VIUF rather than
 their usually going to both.

 On the technical side, last year SNUG'98 had 15 tutorials and 30 user
 papers.  This year, SNUG'99 had 12 tutorials and 35 user papers.  Last
 year, SNUG'98 was 2 1/2 days; this year, SNUG'99 was 3 full days.

   "The presenter gave some interesting statistics for design effort
    at Intel
                  Spec Development   30%
                  Coding             10%
                  Synthesis          15%
                  Design Validation  25%
                  Layout             20%

    I am not sure about the sample size within Intel.  Their initial
    design took 3 months, adding reusability took about 3 weeks, and
    the first re-use of the block took 1 month"

       - Anon

 The Bigwig's Big Speech
 -----------------------

   "I think Aart must be renovating his house these days because his big
    thing this year was comparing every problem the industry is facing to
    various home renovation disasters encountered by 'one of my friends'."

       - Paul Chenard of Hewlett-Packard

 The SNUG'99 keynote address was given, as it always has been, by Aart de
 Geus, the CEO of Synopsys.  This year's speech was very odd in that it was
 a System-On-A-Chip CEO Talk instead of Aart's usual State of the Synopsys
 Union Address.  An awful lot was very conspicuous by its absence from
 Aart's speech.  (For example, *NONE* of the following were mentioned:
 Design Compiler, VSS, behavi{*filter*}synthesis, LMC, Module Compiler, scan
 or ATPG, PrimeTime, MOTIVE, libraries, FPGA synthesis, Formality, ECO
 Compiler, buying/reselling ViewLogic, Protocol Compiler, nor EPIC tools.)

 Here's his speech with all the 'Home Improvement' stories removed.

 About 50% of all semiconductors go into PC's, and the next kill apps for
 semi's are probably Digital TV, Phones, and Internet appliances.  Reuse is
 a big topic since design cannot keep up with Moore's Law of gaining 10X
 gate density every 6 years.  Most systems on a chip (SoC) require both HW
 and SW. The design of these IC's are beginning to merge the styles of ASIC
 flows and Full Custom flows.

 The 3 biggest design challeges are

    1. Specifications and Verification
    2. Timing and Power Closure
    3. IP Reuse

 Here are his views on how each will be solved

   1) Specs and Verification are a big issue with verification being 50% or
      more of the design process.  HW/SW co-simulation will help test SoC.
      Synopsys has a tool called Eagle that is designed for this.

   2) Timing and Power Closure -- Timing is being solved by moving to
      physical synthesis.   A new tool "Chip Architect" is being released
      this year to use placement info in synthesis.  Synopsy has purchased
      a company called Everest, which deleveloped a top level router tool.
      Tool capacity for large chips may be an issue in this area.  Power
      is being solved by Power Compiler and other related tools.

   3) IP reuse is one way to gain productivity. There are 3 kinds of IP

         a) Building Block IP - such as DesignWare
         b) Complex Commodity IP - this is a difficult model to have
                                   a business around.
         c) Star IP - parts like an ARM core that has great IP content.

      Synopsys has published the RMM book and has a MORE rating to gauge
      the goodness of IP.  Some IP companies are having a hard time making
      a business model for commodity IP.  Synopsys wants the DesignWare
      Foundation to always grow over time.

 Synosys also has 2 new testbench tools ( VERA and CoverMeter).  Radiant
 VCS is 3X faster w/ 50% less memory.  There are new IP delivery tools
 called CoreBuilder & CoreConsultant.

 In general, Synopsys 1998 was a $720 M company (3X of its 1993 size) that
 invests 22% back into R&D.  Revenues broke out by

                 North America : #################### 55 - 60 %
                        Europe : ###### 15 - 20 %
                         Japan : ###### 15 - 20 %
                  Asia/Pacific : ## 5 - 10 %

 In a 1998 "EE Times" survey, Synopsys was ranked #1 for customer support,
 Mentor #2, OrCAD #3, Cadence #4.  At the bottom of the 12 company list
 were Summit Design and IKOS.

   "I will forgive not getting to market on time if the reason was to
    make the core reuseable."

       - Brian Halla, CEO of National Semiconductor (as cited by Aart.)

 "WE WANT YOUR FIRST BORN CHILD!"  It's rumored that a woman lawyer inside
 of Synopsys, named Sylvia, who used to work in Licensing Enforcement is
 now heading the Synopsys High School Outreach Program.  "We want to get
 the kids interested in engineering early on.  They're our employees of
 tomorrow!", Sylvia told me.  (And no, I'm not making this up!)

 SELLING ICE TO ESKIMOS  Most companies that do chip design have internal
 networks, internal web sites, with data management and rev control -- yet
 at the Vendor Faire, "Synchronicity" was selling just that.  Selling ice
 to Eskimos?  Wanna buy the Brooklyn bridge?  See www.syncinc.com

 WHY DO THEY WEAR "KICK ME" SIGNS?  At the SNUG R&D faire, Synopsys Customer
 Support had a table with a sign: "Stump The Engineer".  OK, so it looks
 like we customers get to stump them with our tricky Synopsys questions
 face-to-face instead of on the phone.  WRONG!  We were only allowed to
 ask them questions from pre-printed Trivial Pursuit cards!  ("I guess you
 guys still have just as many problems with my bugs whether
...

read more »



Mon, 15 Oct 2001 03:00:00 GMT  
 One Sheep Farmer's Impressions of SNUG'99

Quote:

>>  THE BA{*filter*}T IS FLOODING:  One of the bigger announcements Synopsys
>>  made at SNUG'99 was the how they intended to keep adding more and more
>>  parts to the basic Designware Foundation library.  That is, as a piece
>>  of IP becomes more mainstream in useage, Synopsys is just going to
>>  automatically add it to the Foundation at no extra cost to users.  In
>>  this vein, Aart annouced that the DW PCI core and the DW 8051 were now
>>  part of the DW Foundation library -- free to anyone already using that
>>  library.  This effectively means it's free to anyone using Design
>>  Compiler due to its close ties to the DW Foundation lib!  Way cool!

>Hi!
>First: Thanks for this "assembled newsletter" from SNUG99, John. Good job!

>A lot of good news, especially the one above: the DW PCI core models
>royalty-free in the Foundation lib. Great! But i couldn't find them
>mentioned in the Synopsys news about the new DW features in 1999.05.
>Will they appear in a later release?

>Lars

Lars, I don't know the details other than the fact that Synopsys was putting
the DW 8051 and DW PCI cores into the DW Foundation library.  As far I as I
know, yes, this does mean they're royalty-free (because everything in the
DW Foundation lib is royalty-free) but that doesn't mean they're completely
free.  You still have to *buy* the DW Foundation lib, if you want to use
it.  (Most DC users do buy it, though.)

                                         - John Cooley
                                           the ESNUG guy

============================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 6000+ other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!


     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."



Sun, 21 Oct 2001 03:00:00 GMT  
 One Sheep Farmer's Impressions of SNUG'99

Quote:

> Lars, I don't know the details other than the fact that Synopsys was putting
> the DW 8051 and DW PCI cores into the DW Foundation library.  As far I as I
> know, yes, this does mean they're royalty-free (because everything in the
> DW Foundation lib is royalty-free) but that doesn't mean they're completely
> free.  You still have to *buy* the DW Foundation lib, if you want to use
> it.  (Most DC users do buy it, though.)
>                                          - John Cooley
>                                            the ESNUG guy

That's clear. My question was: When will the 8051 and PCI core be part
of the DW Foundation Lib? Are they available yet? Will they be added to the
current 1999.05 version? Or will they appear in the next major release?
I searched the Synopsys DW webpages, but couldn't find any news about it.
Any infos about this?
I can't wait to get my hands on the PCI core... ;-)

Lars
--
Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/



Mon, 22 Oct 2001 03:00:00 GMT  
 One Sheep Farmer's Impressions of SNUG'99

Quote:
>My question was: When will the 8051 and PCI core be part
>of the DW Foundation Lib? Are they available yet? Will they be added to the
>current 1999.05 version? Or will they appear in the next major release?
>I searched the Synopsys DW webpages, but couldn't find any news about it.
>Any infos about this?
>I can't wait to get my hands on the PCI core... ;-)

Lars,

In the US, these cores are there now in at least some user's Foundation libs
because I've gotten e-mails reporting that DW PCI part in it is encrypted.

                                     - John Cooley
                                       the ESNUG guy

============================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 6000+ other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!


     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."



Fri, 26 Oct 2001 03:00:00 GMT  
 
 [ 4 post ] 

 Relevant Pages 

1. One Sheep Farmer's Impressions of SNUG'99

2. SNUG'99 Boston -- Call For Papers

3. SNUG'99 Boston -- Call For Papers

4. oopsla '99 - DesignFest '99, Call for Problems

5. Reminders: FLoC'99 call for workshops and LICS'98 early registration

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7. Need Your Help Reviewing The SNUG'98 / OVI/VIUF'98 Conferences

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9. Report of the ESUG'99 Seminars

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