clock divider 
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 clock divider

What's an elegant way to code a synthesizable clock divider?

Thanks,

Kru

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Fri, 15 Feb 2002 03:00:00 GMT  
 clock divider

Quote:
> What's an elegant way to code a synthesizable clock divider?

  It is clear to use a kind of counter. The MSB's of counter
  are divided clock outputs.

  It is impractical to use Gray counter or one-hot counter.

  For intermediate clock rates such as 5 MHz - 50 MHz region,
  it is elegant to use a conventional counter.

  If you need several divided clocks with different phases,
  use a Johnson counter. The burden of it is to design the
  counter by yourself. Check if your synthesizer can build
  such counters.

  The other thing is the what kind of restriction does your
  Synthesizer put to your HDL coding. For example, say you
  design an FPGA, Synplify prefers clock dividers as a module
  and in the top level hierarchy.

--
I feel better than James Brown.



Sun, 17 Feb 2002 03:00:00 GMT  
 clock divider
Thanks Utku, this was helpful.



Quote:
>   It is clear to use a kind of counter. The MSB's of counter
>   are divided clock outputs.

<...>

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Sun, 24 Feb 2002 03:00:00 GMT  
 
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