1.Release of "FSM Designer" tool 
Author Message
 1.Release of "FSM Designer" tool

Dear colleagues,

we are very pleased to announce the 1.release of our "FSM Designer"
tool. It lets you specify Finite State Machines in an intuitive
way by graphically editing bubble diagrams. A postprocessor is able
to generate very efficient Verilog HDL code, an ideal base for a
following synthesis step.
Please have a look at the FSM Designer web pages at:

You can download a binary distribution. The tool is written in Java,
conforming to the Java 2 specification. Compute-intensive routines
are provided as shared library, currently available for Sun Solaris.
But we should be able to port the software quickly to other platforms,
perhaps with your help (recompilation of shared library).

We would like to invite you to download and test the software. And we
will be glad about your comments, suggestions etc. It might not be
perfect now, but we are working on improvements and new features
(new output formats: VHDL, Synopsys State Table...).
The FSM Designer is also part of another project, which will allow you
to simulate your FSM's based on earlier simulation runs (VCD data).

The FSM Designer Team

Sun, 10 Jun 2001 03:00:00 GMT  
 [ 1 post ] 

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