Using parameterizable delays in specify blocks ??? 
Author Message
 Using parameterizable delays in specify blocks ???

I am trying to build a generic SRAM model with
parameterizable delays for access time, etc.

However, Verilog-XL complains that numbers used in
$setup, $width, specparam, etc. must be constants.

e.g.
    --------------------------------------
    module sram(addr,data,cs,oe,we);

    defparameter TWE = 10;
    .
    .
    .

    specify
      $width(we,TWE);
    endspecify

    endmodule
    --------------------------------------

does not compile. How can I do this ????

Thanks.
  Stuart Adams



Sat, 13 Feb 1999 03:00:00 GMT  
 Using parameterizable delays in specify blocks ???

:     --------------------------------------
:     module sram(addr,data,cs,oe,we);

:     defparameter TWE = 10;
:     .
:     .
:     .

:     specify
:       $width(we,TWE);
:     endspecify

:     endmodule
:     --------------------------------------

: does not compile. How can I do this ????

Use a specparam inside the specify block.  



Mon, 15 Feb 1999 03:00:00 GMT  
 
 [ 2 post ] 

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