SUMMARY - Control Data Flow Graphs - Languages, Examples and Formats. 
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 SUMMARY - Control Data Flow Graphs - Languages, Examples and Formats.


I had posted a query regarding Languages, examples and formats for
Control data flow graphs. Thanks to everyone who sent me a reply or posted
a followup giving the information. As many people asked me about this
I am posting a summary.

Thanks again

Subject: Control Data Flow Graphs:Languages,Examples,Formats

The Eindhoven/ASCIS DFG format is defined in the technical report
(this may not be the latest version):

  Author        = "J.T.J. van Eijndhoven and G.G. de Jong and L. Stok",
  Title         = "The {ASCIS} Data Flow Graph: Semantics and Textual Format",
  Institution   = "Eindhoven University of Technology",
  Address       = "The Netherlands",
  Number        = "ISBN 90-6144-251-6",
  Year          = "1991"


You should be able to get a copy from Eindhoven without problems. You
could also take a look at their home page:


We've been working on a extension to this graph called the TaoDFG.  It
is being used in various of our synthesis tools, and you can find a
description of the graph in my thesis. Let me know if you're
interested in a copy (I haven't got an on-line copy at the moment).

    Design Automation Group    |constant pain. Between those who run to glory
Department of Computer Science |and those who cannot run. Tell me, which ones
Technical University of Denmark|are the cripples and which ones touch the sky?

Date: Mon, 10 Oct 94 13:18:58 PDT

Subject: Knapp and Parkers representation

Was called DDS (Design Data Structure). Best paper on it
was Knapp and Winslett, IEEE Trans CAD 1990 or thereabouts.
Earliest paper on it was proc. CHDL-85, Elsevier. If you can
get it, tech report DISC-83/6 from USC Dept EE-Systems.


Date: Fri, 7 Oct 94 15:17:34 EDT

Subject: request for info on DFG's

We use dependence flow graphs, which were invented at Cornell by
Prof Keshav Pingali in Computer Science.  These are Control Data Flow
Graphs that have been used extensively for compiler optimizations.  

Dependence flow graphs are used in the Bedroc High Level Synthesis
system at Cornell.

Relevant references are

        title = "High Level Synthesis and Generating {FPGA}'s with the
                {BEDROC} System",
        author = "Miriam Leeser and Richard Chapman and Mark Aagaard and
                Mark Linderman and Stephan Meier",
        journal = "The Journal of {VLSI} Signal Processing",
        year = "1993",
        publisher = "Kluwer Academic Publishers",
        volume = 6,
        number = 2,
        pages = "193 -- 216"

        author = "Richard Chapman and Geoffrey Brown and Miriam Leeser",
        title = "Verified High-Level Synthesis in {BEDROC}",
        booktitle = "Proceedings of 1992 European Design Automation Conference\
        month = "March",
        year = 1992,
        publisher = {IEEE Press},
        pages = "59 -- 63"}

You can get these papers by anonymous ftp from
The first is called, the second is

To get these files:

 # from Unix


 # use "anonymous" when prompted for a name
 # use your login when prompted for a password

 cd pub/hw-verify
 get <filename>         # where <filename> is the complete name
                        # i.e.


To print the file:

 uncompress <filename>.ps.Z

There are also cs techreports on dependence flow graphs available.


Date: Fri, 7 Oct 1994 14:47:13 +0100

Subject: Control Data Flow Graphs:Languages,Examples,Formats

(By the way, your news configuration is broken, this mail bounced:)

>From GMD you can get SIR (System Intermediate Representation), a CDFG format

implemented with persistent C++ classes. We are just in the process of
documenting SIR (in HTML <WWW> format), should be finished in a few weeks. In
the mean time you can ftp the stuff from in de directory
/pub/SYDIS, file sydis.*.tar.gz. There is a daily snapshot of our CVS
directory. It comes with an ANSI-C parser (c2sir ) and a VHDL parser (vh2sir),
as well as a set of tools for dealing with SIR files. (the files that are
dumped by the parsers.) E.g. we have a tool "sirnm" that is the equivalent of
the unix "nm" for object files. And we can graphically display SIR graphs.
And we can ``uncompile'' a SIR file with sir2c or sir2vh. Etc.

Mostly stable, but some tools are still under construction. Graphical stuff is
based on Tcl/Tk and Scheme/Tk, I am not sure if this is also available from the
archive. We use SIR as the heart of our CASTLE codesign environment.

Best regards,

Paul Stravers
           GMD german national research center for computer science

             Schloss Birlinghoven,  53754 Sankt Augustin,  Germany


Date: Thu, 6 Oct 1994 11:56:45 MET

Subject: Control Data Flow Graphs:Languages,Examples,Formats

>From our machine '' you might ftp a report

Furthermore some of our high-level synthesis stuff is available
there in files named neat*
Jos T.J.  van Eijndhoven
Dept. of Elec. Eng.                        phone: +31-40-473612
Eindhoven Univ of Technology, 513  fax:   +31-40-464527


One interesting format which is currently used in compilers,
and can used for synthesis is SUIF: Stanford University Intermediate

It has parsers, data analysis programs and is quite comprehensive.

PS: Try

Since you mentioned Hercules and Yorktown, I assume you're looking for
stuff from High-level/Behavi{*filter*}Synthesis.  If so, I'd add the
internal representation used in the System Architect's Workbench at
CMU: the Value Trace or VT.  It is one of the earliest of the control
data flow graph formats.

The VT is detailed in some of the earlier published papers on SAW.
Don Thomas is coauthor on most SAW papers.  If you're interested and
can't find the papers in your local library, let me know and I can
send you some good references and a tech report order form.


Concerning SAW compilation: You may want to get our new distribution.
We've worked out most of the problems with the contents of the
distribution, and other people have had success compiling it on
SPARCs, HP-PAs, and even PC's under Linux.  The latest and greatest is
at in /Cad_Center/SAW/saw-dist.tar.gz.

The VT does not support events (at least not Verilog events), but you
can poll for action on an input port.  To do specify a
multiple-process behavior, you have to explicitly define the interface
between the processes, which you might want to avoid.  Especially if
you want to use the language for hardware and software process

Tue, 08 Apr 1997 14:19:39 GMT  
 [ 1 post ] 

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