***ANNOUNCEMENT***CMP introducing .18u CMOS*** 
Author Message
 ***ANNOUNCEMENT***CMP introducing .18u CMOS***

     *************************
     ANNOUNCEMENT
     CMP introducing .18u CMOS
     *************************

Washington, USA and Grenoble, France - July 19, 1999 - CMP announced at
the Microelectronics Education Workshop the introduction of
the HCMOS8 .18um CMOS process from STMicroelectronics (Crolles, France).

The HCMOS8 process has the following features :

* Gate length : .18um (drawn), .15um (effective)
* Triple well
* Power supply 1.8 V
* Threshold voltages : VTN = 420 mV,
          VTP = 400 mV


* 6 metal layers + local interconnect
* Low k inter-level dielectric
  Low leakage / low power and 3.3 V power supply options are also
available.

Design kits are supported under Cadence, Synopsys, Eldo and Hspice.

Full custom designs are supported using Virtuoso layout editor and LAS
synthesizer. The layout verifications (DRC, ERC, extraction, LVS) are
fully supported for Diva and Calibre. Transistor-level simulations are
supported under Eldo level 59, and Hspice level 50.

Standard-cell designs are supported using Verilog/VHDL descriptions for
synthesis and simulation. Synthesis is supported under Synopsys.
Simulation is supported under Verilog-XL, Leapfrog and VSS. The
automatic place & route is supported under Silicon Ensemble suite of
tools.

This process is available for prototyping to Education Institutions and
Research Laboratories, on a cooperation basis. No commercial designs are

accepted at this early stage. It is expected that later on, the process
will be available on a commercial basis for small volume production to
Education Institutions, Research Laboratories and specified Companies. A

.15u process would then be made available for Education and Research.

CMP also gave a summary of the achievements to date on the .25u CMOS
process introduced late 1997. A total of 28 projects have been or are
being manufactured. Applications addressed by designers are RF
circuitry, filters, opto-electronic circuitry, characterization,
inductors, analog memories, very complex systems like a neural network
(2.7 million transistors in 11 mm2 from  Helsinky Univ. of Thechnology
in
Finland and a processor in 50 mm2 from LIP6 in France). Institutions
that
submitted circuits are from Denmark, Finland, France, Japan, Sweden,
Switzerland. A total of 80 Institutions have been provided with the
design
rules. It is expected that many more projects will go to fab, after the
Institutions get acquainted with the design flow on deep-submicron, very

different from a micronic or submicronic process.

Also CMP announced that the .25u CMOS process becomes now available on
a more broader basis, in the frame of a deep submicron consulting from
CMP (check with CMP for details).

Finally, CMP announced that an option on the .25u will be available in
Q4 1999 : the metal/metal capacitors option. Such an option will allow
excellent performances for RF designs.

                        **************************

CMP is a broker for a number of technologies (prototyping and low volume

production). Since 1981, 450 Institutions from 40 countries have been
served, through more than 300 runs, 20 semiconductor houses have been
interfaced.

**********************
Integrated circuits :
**********************
AMS 0.8u CMOS DLP/DLM
 0.6u CMOS DLP/TLM
 0.35u CMOS DLP/TLM (4LM)
 0.8u BiCMOS DLP/DLM
 0.8u SiGe HBT-CMOS DLP/DLM

STMicroelectronics 0.18u CMOS 6LM
   0.25u CMOS 6LM

PML 0.2u HEMT GaAs HEMT

*****
MEMS
*****
CMOS and GaAs compatible bulk micromachining
MUMPs from MCNC (Europe, Africa, South America, ...)
DOE from CSEM

***********
Design kits
***********
more than 35 design kits.

********************
MCM and 3D packaging
********************
L, C, D, 3D

********************
CAD software
********************
CADENCE, MEMSCAP, TANNER, ...

********************
Packaging
********************
Ceramic, plastique, for prototyping and low volume production.

*********************************************************
Dr. Kholdoun TORKI       CMP-TIMA  46, Av. Felix Viallet,


Fax : +33 4 76473814                 Tel : +33 4 76574763
*********************************************************



Mon, 11 Feb 2002 03:00:00 GMT  
 ***ANNOUNCEMENT***CMP introducing .18u CMOS***

Quote:

> Design kits are supported under Cadence, Synopsys, Eldo and Hspice.

Not according to the website.  Perhaps it needs some updating?

--
S?ren Laursen http://www.tele.auc.dk/~slau/



Tue, 12 Feb 2002 03:00:00 GMT  
 ***ANNOUNCEMENT***CMP introducing .18u CMOS***

You are right.
We are updating our Web site beginning next week.
Pricing and MPW run schedules will be as well published.

To access to this technology, request has to be sent by E-mail.
Empty form model can be found at :
http://tima-cmp.imag.fr/CMP/ManChap4-F.html   (paragraphe 4.2)

*********************************************************
Dr. Kholdoun TORKI       CMP-TIMA  46, Av. Felix Viallet,


Fax : +33 4 76473814                 Tel : +33 4 76574763
*********************************************************

Quote:


> > Design kits are supported under Cadence, Synopsys, Eldo and Hspice.

> Not according to the website.  Perhaps it needs some updating?

> --
> S?ren Laursen http://www.tele.auc.dk/~slau/



Wed, 13 Feb 2002 03:00:00 GMT  
 
 [ 3 post ] 

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