Combinational logic and gate delays - Help 
Author Message
 Combinational logic and gate delays - Help

Hello All

I have a combinational logic circuit generating a number of waveforms
from the main clock input. There are a number of external inputs to
this circuit controlling the turning on and off of different outputs.

My problem is that I need a certain timing relationship between four of
the outputs.

I realise that normally to obtain a given timing relationship one would
use synchronous logic. But in this case as I require signals with the
same frequency as the main clock I must use combinational logic.

From the output of my logic simulator I am seeing some issues which
confuse me:

(a) Different logic gates have different delays, A NOT has less delay than
    an OR gate. May be this should have been obvious to me. Is it correct?

(b) If I add a gate to create a delay, it seems to be getting optimised out.
    Is there some way to stop a gate added for this purpose from being removed?

Thanks for all assistance in advance.

Denis



Thu, 29 Dec 2005 23:30:22 GMT  
 Combinational logic and gate delays - Help
Denis, I assume (correctly?) that you implement your logic in Xilinx or
Altera FPGAs.
In these parts, the logic is implemented in 4-input look-up tables, and
the distinction between AND, OR, and INV is meaningless. It all ends up
as the through-delay in a ROM with 4 address inputs and thus 16 stored bits.
You can, however, force the software to use one LUT for each gate, but
there still is no systematic difference between different gate types.

I might suggest the clock phase adjust feature in Virtex-II, where you
can define and even step the clock output in increments of (one clock
period divided by 256) or 50 ps. That might give you a far more
predictable solution, and it would be a synchronous design, which we all prefer.

Peter Alfke, Xilinx Applications
============================

Quote:

> Hello All

> I have a combinational logic circuit generating a number of waveforms
> from the main clock input. There are a number of external inputs to
> this circuit controlling the turning on and off of different outputs.

> My problem is that I need a certain timing relationship between four of
> the outputs.

> I realise that normally to obtain a given timing relationship one would
> use synchronous logic. But in this case as I require signals with the
> same frequency as the main clock I must use combinational logic.

> From the output of my logic simulator I am seeing some issues which
> confuse me:

> (a) Different logic gates have different delays, A NOT has less delay than
>     an OR gate. May be this should have been obvious to me. Is it correct?

> (b) If I add a gate to create a delay, it seems to be getting optimised out.
>     Is there some way to stop a gate added for this purpose from being removed?

> Thanks for all assistance in advance.

> Denis



Fri, 30 Dec 2005 08:27:54 GMT  
 Combinational logic and gate delays - Help

Quote:

> I realise that normally to obtain a given timing relationship one would
> use synchronous logic. But in this case as I require signals with the
> same frequency as the main clock I must use combinational logic.

> From the output of my logic simulator I am seeing some issues which
> confuse me:

> (a) Different logic gates have different delays, A NOT has less delay than
>     an OR gate. May be this should have been obvious to me. Is it correct?

> (b) If I add a gate to create a delay, it seems to be getting optimised out.
>     Is there some way to stop a gate added for this purpose from being removed?

Consider using an FPGA with an on-chip PLL.
With a 4x internal clock you might be able
to use the synchonous template for your
design and eliminate those issues.

  -- Mike Treseler



Sat, 31 Dec 2005 00:38:12 GMT  
 Combinational logic and gate delays - Help
Hi Peter

Thanks as always for your help.

I am using a Spartan XL XCS05XL. I dont think features
like that from the Virtex - II are available.

Thanks for the point on the delay. As you can see Im new to
some of the more basic points. Amazing how far you can get
without understanding everything that goes on under the hood.

In the simulation of my final design I can see that signals that
travel through more gates in my schematic have a greater delay. Does this
tie in with the look up table implementation.

Thanks

Denis

Quote:

> Denis, I assume (correctly?) that you implement your logic in Xilinx or
> Altera FPGAs.
> In these parts, the logic is implemented in 4-input look-up tables, and
> the distinction between AND, OR, and INV is meaningless. It all ends up
> as the through-delay in a ROM with 4 address inputs and thus 16 stored bits.
> You can, however, force the software to use one LUT for each gate, but
> there still is no systematic difference between different gate types.

> I might suggest the clock phase adjust feature in Virtex-II, where you
> can define and even step the clock output in increments of (one clock
> period divided by 256) or 50 ps. That might give you a far more
> predictable solution, and it would be a synchronous design, which we all prefer.

> Peter Alfke, Xilinx Applications
> ============================

> > Hello All

> > I have a combinational logic circuit generating a number of waveforms
> > from the main clock input. There are a number of external inputs to
> > this circuit controlling the turning on and off of different outputs.

> > My problem is that I need a certain timing relationship between four of
> > the outputs.

> > I realise that normally to obtain a given timing relationship one would
> > use synchronous logic. But in this case as I require signals with the
> > same frequency as the main clock I must use combinational logic.

> > From the output of my logic simulator I am seeing some issues which
> > confuse me:

> > (a) Different logic gates have different delays, A NOT has less delay than
> >     an OR gate. May be this should have been obvious to me. Is it correct?

> > (b) If I add a gate to create a delay, it seems to be getting optimised out.
> >     Is there some way to stop a gate added for this purpose from being removed?

> > Thanks for all assistance in advance.

> > Denis



Sat, 31 Dec 2005 00:58:32 GMT  
 Combinational logic and gate delays - Help
Hi Peter and All

This implementation and consequent resulting delays issue is begining to
drive me around the bend.

Below is a small diagram of my schematic.
To ensure tha OP2 (Output 2) changes state after OP1 (Output 1)
I set up the circuit as shown.
However I find in my simulation results that OP2 changes state
before OP1.
This appears to defy the laws of physics but Im sure there is a simple
explenation.

Signals control 1 and control 2 are low throughout.

Regards

Denis

                              OP2
    OP1                       _|_
     |                         OR
     |                        |__|
     |                         ||____ control 1
     |                         |
     |_____________| Not |_____|
    _|_
     OR
    |__|
     ||____
     |     |
     |    Not
control2   |
           |
         Main Clk

Quote:

> Denis, I assume (correctly?) that you implement your logic in Xilinx or
> Altera FPGAs.
> In these parts, the logic is implemented in 4-input look-up tables, and
> the distinction between AND, OR, and INV is meaningless. It all ends up
> as the through-delay in a ROM with 4 address inputs and thus 16 stored bits.
> You can, however, force the software to use one LUT for each gate, but
> there still is no systematic difference between different gate types.

> I might suggest the clock phase adjust feature in Virtex-II, where you
> can define and even step the clock output in increments of (one clock
> period divided by 256) or 50 ps. That might give you a far more
> predictable solution, and it would be a synchronous design, which we all prefer.

> Peter Alfke, Xilinx Applications
> ============================

> > Hello All

> > I have a combinational logic circuit generating a number of waveforms
> > from the main clock input. There are a number of external inputs to
> > this circuit controlling the turning on and off of different outputs.

> > My problem is that I need a certain timing relationship between four of
> > the outputs.

> > I realise that normally to obtain a given timing relationship one would
> > use synchronous logic. But in this case as I require signals with the
> > same frequency as the main clock I must use combinational logic.

> > From the output of my logic simulator I am seeing some issues which
> > confuse me:

> > (a) Different logic gates have different delays, A NOT has less delay than
> >     an OR gate. May be this should have been obvious to me. Is it correct?

> > (b) If I add a gate to create a delay, it seems to be getting optimised out.
> >     Is there some way to stop a gate added for this purpose from being removed?

> > Thanks for all assistance in advance.

> > Denis



Sat, 31 Dec 2005 02:30:27 GMT  
 Combinational logic and gate delays - Help
There are a couple of things that can be causing this.

First, you don't mention if you are using synthesis or schematic capture -
if you are using synthesis, then what you are drawing may not be what is
implemented. The basic logic unit in an FPGA is the four input lookup. The
synthesis tool will build "optimal" circuits based on that. Since there are
only three signals here, it is likely that a synthesis tool would implement
OP1 and OP2 independently - so OP2 would be a function of the clock and the
2 control signals, and would NOT use the output of the logic generating OP1.
By the way, gating signals with clocks is also not a really good idea in
FPGAs

Second, a very significant portion of FPGA timing is determined by the
routing, not by the logic implemented. So even if OP2 is fed from the output
of OP1, it is possible that (say) the routing from OP1 to the output pad is
FAR longer than the routing from OP2 to its output pad.

In general, what you are trying to do is NOT recommended - it is VERY
difficult to control the combinational timing of output signals. If you are
comitted to doing this, then you have to control the placer/router to
acheive the desired results. For example, you can put a constraint on OP1
specifying that it should come very quickly after the clock, and a second
constraint on OP2 specifying that it must have a minimum propagation time.
However, FPGA tools are not notoriously good at this, and the mechanism for
specifying these constraints is not trivial. If you are really a {*filter*},
then you can try and place and route the components yourself - that will
lock down the timing, but is INCREDIBLY hard to do! In general you REALLY
don't want to try and control the timing of combinational signals in an FPGA
(or in an ASIC, for that matter, but its a little easier in an ASIC).

Instead of posting questions on how to get the tool to do something it
really doesn't like doing, why don't you broaden the topic and tell us what
you are trying to do - what you are trying to control with this circuit, and
why do you need this timing relationship. There is almost always a way of
doing what you want to accomplish without resorting to controlling
combinational delays.

Avrum


Quote:
> Hi Peter and All

> This implementation and consequent resulting delays issue is begining to
> drive me around the bend.

> Below is a small diagram of my schematic.
> To ensure tha OP2 (Output 2) changes state after OP1 (Output 1)
> I set up the circuit as shown.
> However I find in my simulation results that OP2 changes state
> before OP1.
> This appears to defy the laws of physics but Im sure there is a simple
> explenation.

> Signals control 1 and control 2 are low throughout.

> Regards

> Denis

>                               OP2
>     OP1                       _|_
>      |                         OR
>      |                        |__|
>      |                         ||____ control 1
>      |                         |
>      |_____________| Not |_____|
>     _|_
>      OR
>     |__|
>      ||____
>      |     |
>      |    Not
> control2   |
>            |
>          Main Clk




- Show quoted text -

Quote:
> > Denis, I assume (correctly?) that you implement your logic in Xilinx or
> > Altera FPGAs.
> > In these parts, the logic is implemented in 4-input look-up tables, and
> > the distinction between AND, OR, and INV is meaningless. It all ends up
> > as the through-delay in a ROM with 4 address inputs and thus 16 stored
bits.
> > You can, however, force the software to use one LUT for each gate, but
> > there still is no systematic difference between different gate types.

> > I might suggest the clock phase adjust feature in Virtex-II, where you
> > can define and even step the clock output in increments of (one clock
> > period divided by 256) or 50 ps. That might give you a far more
> > predictable solution, and it would be a synchronous design, which we all
prefer.

> > Peter Alfke, Xilinx Applications
> > ============================

> > > Hello All

> > > I have a combinational logic circuit generating a number of waveforms
> > > from the main clock input. There are a number of external inputs to
> > > this circuit controlling the turning on and off of different outputs.

> > > My problem is that I need a certain timing relationship between four
of
> > > the outputs.

> > > I realise that normally to obtain a given timing relationship one
would
> > > use synchronous logic. But in this case as I require signals with the
> > > same frequency as the main clock I must use combinational logic.

> > > From the output of my logic simulator I am seeing some issues which
> > > confuse me:

> > > (a) Different logic gates have different delays, A NOT has less delay
than
> > >     an OR gate. May be this should have been obvious to me. Is it
correct?

> > > (b) If I add a gate to create a delay, it seems to be getting
optimised out.
> > >     Is there some way to stop a gate added for this purpose from being
removed?

> > > Thanks for all assistance in advance.

> > > Denis



Sat, 31 Dec 2005 03:10:20 GMT  
 Combinational logic and gate delays - Help
A Spartan XL precludes some of the tricks you could have done with a DLL or DCM.  The
problem you are running into is due to the fact that a susbtantial part of the propagation
delay is comprised of routing delays.  Your circuit is most likely being implemented in
two LUTs with parallel inputs.  While the LUT delays are fairly consistent, the delays
incurred in getting the signals to the LUTs and the outputs from the LUTs to the I/O are
in all likelihood not matched.  Unfortunately, the router is not really set up for
matching delays, so you'll probably have to resort to hand routing it using FPGA editor if
this approach is really necessary.  If you could obtain a 2x or 4x clock in the context of
your system, it may be far easier to deal with.  You might also consider using a small
CPLD instead, the routing there is usually less sensitive to the tools.

Quote:

> Hi Peter

> Thanks as always for your help.

> I am using a Spartan XL XCS05XL. I dont think features
> like that from the Virtex - II are available.

> Thanks for the point on the delay. As you can see Im new to
> some of the more basic points. Amazing how far you can get
> without understanding everything that goes on under the hood.

> In the simulation of my final design I can see that signals that
> travel through more gates in my schematic have a greater delay. Does this
> tie in with the look up table implementation.

> Thanks

> Denis


> > Denis, I assume (correctly?) that you implement your logic in Xilinx or
> > Altera FPGAs.
> > In these parts, the logic is implemented in 4-input look-up tables, and
> > the distinction between AND, OR, and INV is meaningless. It all ends up
> > as the through-delay in a ROM with 4 address inputs and thus 16 stored bits.
> > You can, however, force the software to use one LUT for each gate, but
> > there still is no systematic difference between different gate types.

> > I might suggest the clock phase adjust feature in Virtex-II, where you
> > can define and even step the clock output in increments of (one clock
> > period divided by 256) or 50 ps. That might give you a far more
> > predictable solution, and it would be a synchronous design, which we all prefer.

> > Peter Alfke, Xilinx Applications
> > ============================

> > > Hello All

> > > I have a combinational logic circuit generating a number of waveforms
> > > from the main clock input. There are a number of external inputs to
> > > this circuit controlling the turning on and off of different outputs.

> > > My problem is that I need a certain timing relationship between four of
> > > the outputs.

> > > I realise that normally to obtain a given timing relationship one would
> > > use synchronous logic. But in this case as I require signals with the
> > > same frequency as the main clock I must use combinational logic.

> > > From the output of my logic simulator I am seeing some issues which
> > > confuse me:

> > > (a) Different logic gates have different delays, A NOT has less delay than
> > >     an OR gate. May be this should have been obvious to me. Is it correct?

> > > (b) If I add a gate to create a delay, it seems to be getting optimised out.
> > >     Is there some way to stop a gate added for this purpose from being removed?

> > > Thanks for all assistance in advance.

> > > Denis

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950

http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Sat, 31 Dec 2005 04:13:52 GMT  
 Combinational logic and gate delays - Help
Denis, it seems that you are gating the clock. This is not exactly
illegal or immoral, but definitely a bad and dangerous habit. Try to
avoid that. (Use CE instead).

Also remember that the software can compile your combinatorial logic
structure any way it sees fit. In synchronous logic, this does not
matter. But you seem to expect that it does the logic "your way"...
Peter Alfke

Quote:

> Hi Peter and All

> This implementation and consequent resulting delays issue is begining to
> drive me around the bend.

> Below is a small diagram of my schematic.
> To ensure tha OP2 (Output 2) changes state after OP1 (Output 1)
> I set up the circuit as shown.
> However I find in my simulation results that OP2 changes state
> before OP1.
> This appears to defy the laws of physics but Im sure there is a simple
> explenation.

> Signals control 1 and control 2 are low throughout.

> Regards

> Denis

>                               OP2
>     OP1                       _|_
>      |                         OR
>      |                        |__|
>      |                         ||____ control 1
>      |                         |
>      |_____________| Not |_____|
>     _|_
>      OR
>     |__|
>      ||____
>      |     |
>      |    Not
> control2   |
>            |
>          Main Clk


> > Denis, I assume (correctly?) that you implement your logic in Xilinx or
> > Altera FPGAs.
> > In these parts, the logic is implemented in 4-input look-up tables, and
> > the distinction between AND, OR, and INV is meaningless. It all ends up
> > as the through-delay in a ROM with 4 address inputs and thus 16 stored bits.
> > You can, however, force the software to use one LUT for each gate, but
> > there still is no systematic difference between different gate types.

> > I might suggest the clock phase adjust feature in Virtex-II, where you
> > can define and even step the clock output in increments of (one clock
> > period divided by 256) or 50 ps. That might give you a far more
> > predictable solution, and it would be a synchronous design, which we all prefer.

> > Peter Alfke, Xilinx Applications
> > ============================

> > > Hello All

> > > I have a combinational logic circuit generating a number of waveforms
> > > from the main clock input. There are a number of external inputs to
> > > this circuit controlling the turning on and off of different outputs.

> > > My problem is that I need a certain timing relationship between four of
> > > the outputs.

> > > I realise that normally to obtain a given timing relationship one would
> > > use synchronous logic. But in this case as I require signals with the
> > > same frequency as the main clock I must use combinational logic.

> > > From the output of my logic simulator I am seeing some issues which
> > > confuse me:

> > > (a) Different logic gates have different delays, A NOT has less delay than
> > >     an OR gate. May be this should have been obvious to me. Is it correct?

> > > (b) If I add a gate to create a delay, it seems to be getting optimised out.
> > >     Is there some way to stop a gate added for this purpose from being removed?

> > > Thanks for all assistance in advance.

> > > Denis



Sat, 31 Dec 2005 06:21:33 GMT  
 Combinational logic and gate delays - Help
Denis, you may just have been lucky. The software can pack any logic
with four inputs and one output into one LUT, with almost the same dalay.
Don't assume blindly that more logic always means a longer delay...
Peter Alfke
===========
Quote:

> In the simulation of my final design I can see that signals that
> travel through more gates in my schematic have a greater delay. Does this
> tie in with the look up table implementation.

> Thanks

> Denis



Sat, 31 Dec 2005 06:15:47 GMT  
 Combinational logic and gate delays - Help

Quote:
>This implementation and consequent resulting delays issue is begining to
>drive me around the bend.
>Below is a small diagram of my schematic.
>To ensure tha OP2 (Output 2) changes state after OP1 (Output 1)
>I set up the circuit as shown.
>However I find in my simulation results that OP2 changes state
>before OP1.
>This appears to defy the laws of physics but Im sure there is a simple
>explenation.

The fundamental problem is that the tools don't support what you are
trying to do.  And if you need a minimum delay, the silicon doesn't
really support it either.

When you draw a pile of gates like that, the system tosses them in
the air and comes up with an equivalent circuit that usually fits
better in the part.  While doing that, it doesn't worry about
relative timing.  It's just trying to meet setup times for the
next clock.  It often makes copies of your "gates" since they are
free if the LUT has unused inputs.

Have you tried the floorplanner or such to see what they actually did?

The first approach is to find some way to do the job with "simple"
cleanly clocked logic.  That's what the tools expect you to be doing.
If you can get a 2x clock, then you can put a FF after the OR gate for
OP1, (and fixup the logic) and then run that signal over to the
gate for OP2.  That doesn't guarantee that OP1 will get to the outside
world before OP2.  Can you add a half clock (double clock?) delay?  If
so, add a FF on OP2 and clock it on the other edge.  If you really
want clean timings on the outside world, you want to use FFs in the
IOBs.  (perhaps cloning the logic, so you have a copy inside to
feed to other logic)

You probably CAN trick the tools into doing something useful, but you
will have problems like this, and if you change anything or the tools
change, you might have to go through this all over again.

It's an interesting chicken-egg problem.  Because the tools don't
support this sort of thing, not many people try to do it.  Since
not many people do it, there is no demand for the tools to support it.

Do you have spare IO pins?  One thing you can do is bring OP1 out
on one pin and back in on another without telling the system about
the external connection.  You can probably bring it back in on the
same pin, but now you are taking the risk that some smart tool will
see what you are doing and "fix" it up for you.

--
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.



Sun, 01 Jan 2006 10:31:26 GMT  
 Combinational logic and gate delays - Help
Hi Guys

Many thanks for all the input.
Its given me loads to mull over.
Ill do some more work and get back to you all.

Regards and thanks

Denis

Quote:


> > I realise that normally to obtain a given timing relationship one would
> > use synchronous logic. But in this case as I require signals with the
> > same frequency as the main clock I must use combinational logic.

> > From the output of my logic simulator I am seeing some issues which
> > confuse me:

> > (a) Different logic gates have different delays, A NOT has less delay than
> >     an OR gate. May be this should have been obvious to me. Is it correct?

> > (b) If I add a gate to create a delay, it seems to be getting optimised out.
> >     Is there some way to stop a gate added for this purpose from being removed?

> Consider using an FPGA with an on-chip PLL.
> With a 4x internal clock you might be able
> to use the synchonous template for your
> design and eliminate those issues.

>   -- Mike Treseler



Sun, 01 Jan 2006 21:49:03 GMT  
 Combinational logic and gate delays - Help
Mike et al -

one of the things that you are running into is caused by the router and
the part - these LUT based models cannot be accurately simulated to this
point because you end up hand routing and then running simulations in a
circle - I end up using Actel SX parts for critical timing (they have
very deterministic delays through all of the cells that allow you to do
this).  I like Xilinx and Altera parts very much, but they have
limitations, and timing accuracy is one of them.  Consider the
architecture of the part when you decide on your needs.

Quote:


>> I realise that normally to obtain a given timing relationship one would
>> use synchronous logic. But in this case as I require signals with the
>> same frequency as the main clock I must use combinational logic.

>> From the output of my logic simulator I am seeing some issues which
>> confuse me:

>> (a) Different logic gates have different delays, A NOT has less delay
>> than
>>     an OR gate. May be this should have been obvious to me. Is it
>> correct?

>> (b) If I add a gate to create a delay, it seems to be getting
>> optimised out.
>>     Is there some way to stop a gate added for this purpose from
>> being removed?

> Consider using an FPGA with an on-chip PLL.
> With a 4x internal clock you might be able
> to use the synchonous template for your
> design and eliminate those issues.

>  -- Mike Treseler



Mon, 02 Jan 2006 12:33:20 GMT  
 Combinational logic and gate delays - Help
Hi Andrew,

Quote:
> one of the things that you are running into is caused by the router and
> the part - these LUT based models cannot be accurately simulated to this
> point because you end up hand routing and then running simulations in a
> circle - I end up using Actel SX parts for critical timing (they have
> very deterministic delays through all of the cells that allow you to do
> this).  I like Xilinx and Altera parts very much, but they have
> limitations, and timing accuracy is one of them.  Consider the
> architecture of the part when you decide on your needs.

I am unfamiliar with these parts, but I took a peak through the datasheet,
and I don't see what it is that would make these chips any more
deterministic than other FPGAs (especially non-segmented ones like FLEX10K,
APEX20K, etc.).  Can you elaborate?

One thing to be aware of is that what the software tells you is the delay of
an element may not be very accurate at all -- the goal of FPGA software is
to ensure that your design runs correctly at the frequency reported.  There
are numerous effects that can either be swept under the rug (and covered by
guard-band/conservative results) or modeled accurately.  Some things I can
think of off the top of my head:

- Skew along a routing wire (the further you go, the longer it takes).
Small effect on short wires though...
- Loading effects (the more active loads on a wire, the slower it is)
- Rise/Fall delay (usually rise and fall are not perfectly matched; software
can't figure out which you care about, reports max)
- Assymetries in the combinational logic (some paths may be faster than
others due to circuit design).
- Edge rates (depending on path taken, may have different edge rate, but
software may just model a single, worst-case edge rate)
- Proximity effects in layout.  Though all wires may look the same, are
they?  Depending on neighbouring metal, some wires may have higher/lower R &
C for a variety of reasons.  Does the software model them as such?
- Other subtle differences in layout.

This means that though one part may *appear* more deterministic, this may
just be a sign of a less sophisticated timing model.  I'm not saying that's
the case for SX (I have no clue), but just someting to be aware of in
general.

As previously indicated by posters, relying on a particular delay to be
predictable is not a good.  Process, temperature and voltage variation make
it next to impossible to do so.  The "-7" chip you have may be a "-5" chip
that has been down-binned.  Tools usually report the delay assuming
worst-case temperature, voltage, IR drop, silicon that is at the edge of the
bin, etc.

Regards,

Paul Leventis
Altera Corp.



Mon, 02 Jan 2006 20:47:54 GMT  
 
 [ 13 post ] 

 Relevant Pages 

1. This week's Coding tip: modeling combinational logic with inertial delays

2. This week's Coding tip: modeling combinational logic with inertial delays

3. Delay in logic gates!

4. wire and reg and modelling of combinational logic

5. feed back of combinational logic.

6. How to eliminate glitches for combinational logic design

7. feedback input with combinational logic!

8. question on combinational logic synthesis for FPGA

9. Gate delay suggestions

10. Delta Delays with gated clocks

11. Gate delay suggestions

12. Modeling a tran gate (bidir wire delay) in VHDL

 

 
Powered by phpBB® Forum Software