conditional signal assignment 
Author Message
 conditional signal assignment

Hi,

    In verilog, is it possible to write a conditional signal assignment
using combinational logic?  I tried to write it this way, but it didn't work

module csa(data_in, sel, data_out);
    input [3:0] data_in;
    input [1:0] sel;
    output data_out;

    case (sel)
        2'b00: data_out = data_in[0];
        2'b01: data_out = data_in[1];
        2'b10: data_out = data_in[2];
        2'b11: data_out = data_in[3];
    endcase
endmodule

it gives the following error message while using Active-HDL compiler...

Error: VCP2000 csa.v : (6, 9): Syntax error. Unexpected token: case[_CASE].
Expected tokens: 'endmodule' , 'always' , 'and' , 'assign' , 'buf' ... .

    The conditional signal assignment in VHDL can be written as the
following

    data_out <= data_in(0) when sel = "00" else
                        data_in(1) when sel = "01" else
                        data_in(2) when sel = "10" else
                        data_in(3);

   How about Verilog???



Sun, 05 Oct 2003 10:06:17 GMT  
 conditional signal assignment


Quote:
>Hi,

>    In verilog, is it possible to write a conditional signal assignment
>using combinational logic?  I tried to write it this way, but it didn't work

>module csa(data_in, sel, data_out);
>    input [3:0] data_in;
>    input [1:0] sel;
>    output data_out;

>    case (sel)
>        2'b00: data_out = data_in[0];
>        2'b01: data_out = data_in[1];
>        2'b10: data_out = data_in[2];
>        2'b11: data_out = data_in[3];
>    endcase
>endmodule

>it gives the following error message while using Active-HDL compiler...

You are very close actually. You just have to put the case statement
in an always block:

reg data_out;


begin
    case (sel)
        2'b00: data_out = data_in[0];
        2'b01: data_out = data_in[1];
        2'b10: data_out = data_in[2];
        2'b11: data_out = data_in[3];
    endcase
end

begin;end pair is not necessary here but is a precaution for future
changes.

Muzaffer

FPGA DSP Consulting
http://www.dspia.com



Sun, 05 Oct 2003 11:55:57 GMT  
 conditional signal assignment
Thanks for your help, muzaffer!

I noticed that you have added ...

reg data_out;

and used...


Will that generate latch?

In my original design, it is 4-1 MUX (did not compile).  but let say I want
to have a simple 2-to-1 MUX  ...and I would write the following code:

module mux2_1(data_in, sel, data_out);
    input [1:0] data_in;
    input sel;
    output data_out;

assign data_out = (sel)? data_in[0] : data_out[1];

endmodule

Please note that... data_out is just 'wire', but not 'reg'... and also I
don't have to use 'always' here?

since the concept for the two mux are the same... why one uses 'reg'... and
the other uses 'wire'

correct me if I am wrong since I just started coding around with verilog.


Quote:


> >Hi,

> >    In verilog, is it possible to write a conditional signal assignment
> >using combinational logic?  I tried to write it this way, but it didn't
work

> >module csa(data_in, sel, data_out);
> >    input [3:0] data_in;
> >    input [1:0] sel;
> >    output data_out;

> >    case (sel)
> >        2'b00: data_out = data_in[0];
> >        2'b01: data_out = data_in[1];
> >        2'b10: data_out = data_in[2];
> >        2'b11: data_out = data_in[3];
> >    endcase
> >endmodule

> >it gives the following error message while using Active-HDL compiler...

> You are very close actually. You just have to put the case statement
> in an always block:

> reg data_out;


> begin
>     case (sel)
>         2'b00: data_out = data_in[0];
>         2'b01: data_out = data_in[1];
>         2'b10: data_out = data_in[2];
>         2'b11: data_out = data_in[3];
>     endcase
> end

> begin;end pair is not necessary here but is a precaution for future
> changes.

> Muzaffer

> FPGA DSP Consulting
> http://www.dspia.com



Sun, 05 Oct 2003 12:37:30 GMT  
 conditional signal assignment


Quote:
>Thanks for your help, muzaffer!

>I noticed that you have added ...

>reg data_out;

>and used...


>Will that generate latch?

>In my original design, it is 4-1 MUX (did not compile).  but let say I want
>to have a simple 2-to-1 MUX  ...and I would write the following code:

>module mux2_1(data_in, sel, data_out);
>    input [1:0] data_in;
>    input sel;
>    output data_out;

>assign data_out = (sel)? data_in[0] : data_out[1];

>endmodule

>Please note that... data_out is just 'wire', but not 'reg'... and also I
>don't have to use 'always' here?

>since the concept for the two mux are the same... why one uses 'reg'... and
>the other uses 'wire'

In Verilog, not all "reg"s are hardware registers. Some registers are
actually wires (or nets) and they generate combinational hardware. The
case statement in question should not generate a latch because
data_out is assigned in all paths. IOW, for all combinations of sel,
data_out is assigned so there is no need for a latch.
Actually a conditional assignment doesn't guarantee combinational
code. You can code a latch with it too. This is becase
assign data_out = sel ? data_in[1] : data_in[0];
is equivalent to

if (sel)
        data_out = data_in[1];
else
        data_out = data_in[0];

so
assign latch = sel ? in : latch;
will generate a latch  just as

if (sel)
        data_out = data_in;

will.

One way to use an assignment for a multi-bit mux is to write a
function and call it in the assignment.

Muzaffer

FPGA DSP Consulting
http://www.dspia.com



Sun, 05 Oct 2003 14:22:10 GMT  
 
 [ 4 post ] 

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