Data transitioning clock domains... 
Author Message
 Data transitioning clock domains...

Hey all,

What is the best way to transfer data from 2 different clock domains?
Say I have 8 bits I receive at 33 MHz on one bus and want to put it on
another bus at 25MHz? Any suggestions on how to do this?

Thanks in advance,

Todd Lawson

--
M. Todd Lawson                                (408)371-8245 x102
InterProphet Corporation,                     Campbell CA              
Member of Technical Staff



Mon, 14 Aug 2000 03:00:00 GMT  
 Data transitioning clock domains...

Quote:

> Hey all,

> What is the best way to transfer data from 2 different clock domains?
> Say I have 8 bits I receive at 33 MHz on one bus and want to put it on
> another bus at 25MHz? Any suggestions on how to do this?

Depending on the actual nature of the hardware, my first inclination
would be to use a parallel shift registers in each direction, using both
clock domains; transmit with one clock and receive with the other. You
could either arbitrate the clocks, or use an "interrupt/acknowledge"
protocal.

or...  use an asynchronous serial link, similar to RS232.



Mon, 14 Aug 2000 03:00:00 GMT  
 Data transitioning clock domains...

Quote:


>> Hey all,

>> What is the best way to transfer data from 2 different clock domains?
>> Say I have 8 bits I receive at 33 MHz on one bus and want to put it on
>> another bus at 25MHz? Any suggestions on how to do this?

>Depending on the actual nature of the hardware, my first inclination
>would be to use a parallel shift registers in each direction, using both
>clock domains; transmit with one clock and receive with the other. You
>could either arbitrate the clocks, or use an "interrupt/acknowledge"
>protocal.

That is a good idea, but it would add significant delay between the
transitions: clock data in at 33, set a "data available bit", read the
data at 25 MHz, clear the data available bit. About 4 clock cycles per
transfer. The application for this is a Media Access Controller for a
network interface card. Network data is clocked in with the RX clock,
then the data is read from a fifo at the system clock. How about a 3+
deep circular fifo, with writes on oner clock, reads on the other
clock, with control logic to manage the pointers and the pointer creep
you would have? That would be simple in the fast clock read, slow
clock write instance, a bit more complicated in the opposite.

Any fine tune suggestions?

Todd

--
M. Todd Lawson                                (408)371-8245 x102
InterProphet Corporation,                     Campbell CA              
Member of Technical Staff



Mon, 14 Aug 2000 03:00:00 GMT  
 Data transitioning clock domains...

Excelent Idea, But don't you think a FIFO would do it better?

Zade Samuel



Mon, 21 Aug 2000 03:00:00 GMT  
 
 [ 4 post ] 

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