+define+unknown="'bx" chokes verilog 
Author Message
 +define+unknown="'bx" chokes verilog

Hi,

Wonder if someone has run into this before.
The above define causes tremendous headaches
in my csh script regardless of what manner of quotes
or not that I use, and regardless of what manner of
backslach in front of the apostrophe I use.  The
problem remains the same even if I use the
definition 32'bx .

I even
tried defining "unknown" in the source code itself,
and referencing it with +define+WhatNow="`unknown",
but again, the same headaches with the backward
apostrophe.

I tried verilogXL and ncverilog on solaris 8.
Has anyone ever gotten such a thing to work?
The usage is not that bizzare...

Thanks,

Fred

--------------------------------------------------------------------------
Fred Ma
Department of Electronics
Carleton University, Mackenzie Building
1125 Colonel By Drive
Ottawa, Ontario
Canada     K1S 5B6

==========================================================================



Mon, 12 Jul 2004 18:00:16 GMT  
 +define+unknown="'bx" chokes verilog

Quote:
> Hi,

> Wonder if someone has run into this before.
> The above define causes tremendous headaches
> in my csh script regardless of what manner of quotes

I never use csh(1) so I can't comment on its quoting rules.

Quote:
> and referencing it with +define+WhatNow="`unknown",

bash will try to match the `. If you want to pass exactly the above to
your simulator you have to write (again bash):

+define+WhatNow=\"\`unknown\"

The shell will process your command line arguments before they are
passed to the simulator. Try to compile this hello world style program
and see what you actually are passing to your simulator:

   #include <stdio.h>

   int main(int argc,char** argv) {
     int i;
     for (i=0; i<argc; i++) {
       printf("argc[%d]=<%s>\n",i,argv[i]);
     }
     return 0;
   }

An example:

   module what;

   initial begin
      $display("value is %b",`unknown);
   end

   endmodule

   verilog +define+unknown=32\'bx hello.v

Gives:
value is xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx

Petter
--
1)
 The only way tcsh "rocks" is when the rocks are attached to its feet
 in the deepest part of a very deep lake.             (Linus Torvalds)
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com



Mon, 12 Jul 2004 18:54:29 GMT  
 +define+unknown="'bx" chokes verilog
Hi (again) Fred,
                    I am not sure if I understood your problem, but
the following works for me:

-- ****** Code *******
module test;

initial
begin
  `ifdef unknown // = "'bx"
    $display ("BX ",`unknown);
  `else
    $display ("NO BX");
  `endif
end
endmodule

// +define+unknown="'bx" chokes verilog

-- ****** Code*******

I run this as:

verilog +define+unknown="'bx" ../RTL/define.v

(I use KSH BTW).

The above command prints:

-- ****** log *******

Compiling source file "../RTL/define.v"
Highest level modules:
test

BX          x
0 simulation events (use +profile or +listcounts option to count)

-- ****** ENd of log *******

  Is this somewhat close to what you intended or am I totally off the
way from your problem?

Regards,
Srinivasan



Quote:
> Hi,

> Wonder if someone has run into this before.
> The above define causes tremendous headaches
> in my csh script regardless of what manner of quotes
> or not that I use, and regardless of what manner of
> backslach in front of the apostrophe I use.  The
> problem remains the same even if I use the
> definition 32'bx .

> I even
> tried defining "unknown" in the source code itself,
> and referencing it with +define+WhatNow="`unknown",
> but again, the same headaches with the backward
> apostrophe.

> I tried verilogXL and ncverilog on solaris 8.
> Has anyone ever gotten such a thing to work?
> The usage is not that bizzare...

> Thanks,

> Fred

--
Srinivasan Venkataramanan
ASIC Design Engineer
Software & Silicon Systems India Pvt. Ltd. (An Intel company)
Bangalore, India, Visit: http://www.simputer.org)
"I don't Speak for Intel"


Mon, 12 Jul 2004 19:31:53 GMT  
 +define+unknown="'bx" chokes verilog
I just tried the shells and backslashed quotes
suggested in your replies....no luck, but I
think I know why.  Iuse verilog at more than
one location, each has a different shell for
the verilog and ncverilog scripts (that's another
thing that complicates the problem, I'm
invoking scripts rather than the executable
itself).

One thing that did work partially was
+define+unknown=\"\'bx\", except the
$displayed result is a random 32-bit sequence
of 0's and 1's rather than x.  If I supply a
non-x definition, it passes through to the
simulation, it's only when I use 'bx
(including \"32\'bx\").

Because I have an intermediate script
between my script and the executable,
and because that script's shell is not
consistent from one location to another,
I'm not sure if it's fruitful to try resolving
the comand line argument passing.  What
I've done is to stick the definition of `unknown
in an include file, and I just change it right there.

Thanks for your suggesttions.

Fred
--------------------------------------------------------------------------
Fred Ma
Department of Electronics
Carleton University, Mackenzie Building
1125 Colonel By Drive
Ottawa, Ontario
Canada     K1S 5B6

==========================================================================



Tue, 13 Jul 2004 08:06:44 GMT  
 +define+unknown="'bx" chokes verilog

Quote:
> think I know why.  Iuse verilog at more than
> one location, each has a different shell for
> the verilog and ncverilog scripts (that's another
> thing that complicates the problem, I'm
> invoking scripts rather than the executable
> itself).

This can complicate things a bit, especially if you have several
levels of scripts (even different types of shells) calling each other.
It also depends on how you quote your arguments to your simulator.

Quote:
> I've done is to stick the definition of `unknown
> in an include file, and I just change it right there.

I don't like include files. I prefer to put most of my backticks in a
separate file which is the first file passed to the simulator. It's
also the first file I read in my synthesis scripts.

Petter
--
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com



Tue, 13 Jul 2004 15:03:22 GMT  
 +define+unknown="'bx" chokes verilog

I agree with collecting all the backticks into a file...that's basically
what I'm doing with the include file....

Fred
--------------------------------------------------------------------------
Fred Ma
Department of Electronics
Carleton University, Mackenzie Building
1125 Colonel By Drive
Ottawa, Ontario
Canada     K1S 5B6

==========================================================================

Quote:


> > think I know why.  Iuse verilog at more than
> > one location, each has a different shell for
> > the verilog and ncverilog scripts (that's another
> > thing that complicates the problem, I'm
> > invoking scripts rather than the executable
> > itself).

> This can complicate things a bit, especially if you have several
> levels of scripts (even different types of shells) calling each other.
> It also depends on how you quote your arguments to your simulator.

> > I've done is to stick the definition of `unknown
> > in an include file, and I just change it right there.

> I don't like include files. I prefer to put most of my backticks in a
> separate file which is the first file passed to the simulator. It's
> also the first file I read in my synthesis scripts.

> Petter
> --
> ________________________________________________________________________
> Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog  http://gustad.com



Wed, 14 Jul 2004 07:44:16 GMT  
 
 [ 6 post ] 

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