Qualis Verilog Training Course, Beaverton, OR 
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 Qualis Verilog Training Course, Beaverton, OR

  This course is intended for hardware and software engineers who
  need to understand Verilog, HDL-based design methods, and coding
  for synthesis, while minimizing ramp-up time.

  "Verilog: A Comprehensive Introduction for Top Down Design"
  -----------------------------------------------------------
        "Verilog: A Comprehensive Introduction for Top Down Design" is a
        fast paced, 5-day hands-on, multi-media course designed not only
        to teach the entire Verilog language, but to make class
        participants immediately productive in a synthesis and system
        simulation environment using state-of-the-art tools.

        Students will have access to individual Sun Sparcstations, the
        Verilog simulation environment, and the Synopsys DC Expert
        synthesis environment for use during the laboratory sessions.  
        After an introduction to Verilog, the course deviates from the
        traditional bottom-up, gates-to-behavi{*filter*}modeling presentation
        of course materials and reverses the flow, teaching top-down
        design practices, with early special emphasis on coding for
        synthesis, efficient testbench generation and advanced design
        verification techniques. These skills are reinforced throughout
        the week while teaching Verilog from a top-down perspective.

  About the Verilog Instructor
  ----------------------------
        "Verilog: A Comprehensive Introduction for Top Down Design" is
        taught by Cliff Cummings, Qualis Director of Training and a
        Principal Engineer who has completed many ASIC and FPGA designs
        and system simulation projects. Mr. Cummings is capable of
        answering the very technical questions asked by experienced
        design engineers.

        Mr. Cummings is a principal member of the IEEE 1364 Verilog
        Standardization committee and has taught dozens of Verilog
        classes and advanced Verilog HDL seminars. He has also presented
        eight papers on topics including ASIC test vector generation,
        FPGA design methodologies, Verilog passive device modeling, board
        test generation techniques, and inter-tool flow for system
        simulation. Two of Mr. Cummings' works were voted Best Paper at
        the 1993 and 1994 International Cadence Users Conferences.

        Mr. Cummings, who holds a BSEE from Brigham Young University and
        an MSEE with Computer Science minor from Oregon State University,
        is a member of the IEEE and the Eta Kappa Nu, Tau Beta Pi and
        Sigma Delta Pi Honor Societies.

  About Qualis Design Corporation
  -------------------------------
        Qualis Design Corporation is the leading independent provider of
        top-down consulting, design, and training services.  The company
        provides services to leading-edge high technology firms worldwide.

        Qualis HDL Training Courses are conducted on leading-edge Sun
        workstations using the latest EDA vendor tools, and are taught by
        engineering professionals with extensive digital design
        experience.  Engineers who complete the Qualis VHDL & Verilog
        Training Courses will be more efficient users of system
        simulation tools, will be capable of implementing advanced
        simulation environments, and will have the knowledge to
        successfully complete complex design projects.  Engineers with
        previous exposure to VHDL and Verilog will also benefit from the
        leading-edge material presented.

  Additional Information
  ----------------------
        The Verilog course is a five day course.

        Complimentary continental breakfast, a full lunch and afternoon
        refreshments are provided for each day of the class.  The next
        regularly scheduled class date is:

        "Verilog: A Comprehensive Introduction for Top Down Design"
                Class Dates:    May 15-19
                Time:           8:30 AM to 5:00 PM

        Class Location:
                Residence Inn, Portland West
                Just West of Beaverton, OR

        For more information about this course, including course
        description and syllabus', contact us at:

                            Qualis Design Corporation
                           15455 NW Greenbrier Parkway
                                   Suite 250
                              Beaverton, OR  97006

                             Phone: (503) 531-0377

  ----------------------------------------------------------------------------

  Copyright (c) 1995 Qualis Design Corporation.  All rights reserved.

  "DC Expert" is a trademark of Synopsys, Incorporated
  "Verilog" is a registered trademark of Cadence Design Systems



Wed, 15 Oct 1997 03:00:00 GMT  
 
 [ 1 post ] 

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