How to: Concise architec desc of repeated gates 
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 How to: Concise architec desc of repeated gates


Quote:

>Is there any concise way to do an architectural description of a large
>number of simiar gates? For example, I want to write an AND-structure
>which ANDs two 8bit numbers using 2input AND gates. Is there any way to
>represent the following in a concise form:

>and g0(out[0], in1[0], in2[0]);
>and g1(out[1], in1[1], in2[1]);
>..
>..
>and g7(out[7], in1[7], in2[7]);

>I need an architectural desc, so 'out = in1 & in2' is not useful to me.

You can use:

and g [7:0] (out, in1, in2);

to generate 8 instances on an "and" gate where each of the inputs and outputs is also an array [7:0].

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Fri, 20 Aug 1999 03:00:00 GMT  
 How to: Concise architec desc of repeated gates

While teaching an onsite Verilog-Synthesis Course in the past month, I
noticed that the most recent version of Verilog-XL (version unknown) now does
Array-Of-Instance for Verilog gate primitives. I believe SILOS III also does
Array-Of-Instance on gate primitives as well, and other Verilog vendors may
have similarly implemented this new functionality, which is defined in the
IEEE-1364 Verilog LRM. This functionality is not yet synthesizable by
Synopsys, but the structure is:

wire [7:0] out, in1, in2;
and g[7:0] (out, in1, in2);

Perhaps other kind newsgroup readers could post which versions of Verilog
simulators now accept this syntax. Note: Verilog-XL does not yet allow
Array-Of-Instance constructs on user defined modules (I am looking forward to
that enhancement).

Since you are at a University, you may not be running the latest and greatest
Verilog-XL   :-(

Regards - Cliff Cummings

Quote:

> HI

> Is there any concise way to do an architectural description of a large
> number of simiar gates? For example, I want to write an AND-structure
> which ANDs two 8bit numbers using 2input AND gates. Is there any way to
> represent the following in a concise form:

> and g0(out[0], in1[0], in2[0]);
> and g1(out[1], in1[1], in2[1]);
> .
> .
> and g7(out[7], in1[7], in2[7]);

> I need an architectural desc, so 'out = in1 & in2' is not useful to me.

> Thanks in advance for your comments and suggestions.

> Bye
> Dipankar Talukdar
> Dept of Elect and Comp Engg
> State Univ of New York at Buffalo

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Fri, 20 Aug 1999 03:00:00 GMT  
 How to: Concise architec desc of repeated gates

Quote:

: dipankar talukda writes:

: Is there any concise way to do an architectural description of a large
: number of simiar gates? For example, I want to write an AND-structure
: which ANDs two 8bit numbers using 2input AND gates. Is there any way to
: represent the following in a concise form:
:
: and g0(out[0], in1[0], in2[0]);
: and g1(out[1], in1[1], in2[1]);
: .
: .
: and g7(out[7], in1[7], in2[7]);
:
: I need an architectural desc, so 'out = in1 & in2' is not useful to me.
:
: Thanks in advance for your comments and suggestions.
:
: Bye
: Dipankar Talukdar
: Dept of Elect and Comp Engg
: State Univ of New York at Buffalo
:      
        As has been noted, few tools support the new arrays of
instances construct; and even then, it perhaps is not as powerful as
you would like (try building wallace trees..)

        Until then, you can use the verilog preprocessor, written by
Himanshu M. Thaker, which is described, and is available from my web
site, at <http://www-silicon-sorcery.com>

--
Michael McNamara Silicon Sorcery [37 15.7878' -121 57.4658'] Get my
verilog emacs mode (subscribe for free updates!) at
             <http://www.silicon-sorcery.com/verilog-mode.html>



Sat, 21 Aug 1999 03:00:00 GMT  
 
 [ 3 post ] 

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