Inertial and transport delay in Verilog
Author Message
Inertial and transport delay in Verilog

I am learning Verilog. However, I have a
fair knowledge of VHDL.

VHDL provides two delay models - inertial
and transport delay models.

Verilog does not have the keywords
"inertial" and "transport".

What is the delay model used in a
continuous assignment statement ?

assign #5 x = a & b;

If it is the transport delay model,
how to specify the use of the inertial delay
model ? If it is the inertial delay model,
how do we specify the use of the transport
delay model ?

It would be helpful if anyone can provide
the Verilog-equivalent of the following
VHDL description.

===============================================
entity NAND_gate is
port (A : in BIT;
B : in BIT;
Z : out BIT);
end NAND_gate;

architecture ARC_transport of NAND_gate is
begin
Z <= A nand B transport after 5 ns;
end;

architecture ARC_inertial of NAND_gate is
begin
Z <= A nand B after 5 ns;
end;
================================================

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Tue, 11 Dec 2001 03:00:00 GMT
Inertial and transport delay in Verilog
I think this simple example will illustrate the concept.

//***************************************************
module delay(in,transport,inertial);
input in;
output transport;
output inertial;

reg   transport;
wire   inertial;

// behaviour of delays

begin
transport <= #10 in;
end

assign #10 inertial = in;

endmodule // delay
//**********************************************
_______     __
in         _____|     |_____||_______

_______     __
transport  _________|     |_____||_____

_______
inertial   _________|     |____________

Non blocking assignment gives you transport delay.
Whenever input changes, output is immediately evaluated
and kept in a event queue and assigned to output
after specified "transport" delay.

In Continuous assign statement the latest event
overrides the earlier event in the queue.

I am attaching rudimentary testbench and its output.
Hope this helps.

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Rajesh Ba{*filter*}ule

module test;
reg  in;
wire transport, inertial;

// instantiate delay module
delay my_delay(in,transport,inertial);

// apply inputs
initial
begin
in = 0;
#20 in = 1;
#20 in = 0;
#30 in = 1;
#5  in = 0;
#30 in = 1;
#30 \$finish;
end
// monitor signals
initial
begin
\$monitor(\$time,"  in = %b  transport = %b inertial = %b",
in,transport, inertial);
end

endmodule // test

//************ log file
Compiling source file "delay.v"
Highest level modules:
test

0  in = 0  transport = x inertial = x
10  in = 0  transport = 0 inertial = 0
20  in = 1  transport = 0 inertial = 0
30  in = 1  transport = 1 inertial = 1
40  in = 0  transport = 1 inertial = 1
50  in = 0  transport = 0 inertial = 0
70  in = 1  transport = 0 inertial = 0
75  in = 0  transport = 0 inertial = 0
80  in = 0  transport = 1 inertial = 0
85  in = 0  transport = 0 inertial = 0
105  in = 1  transport = 0 inertial = 0
115  in = 1  transport = 1 inertial = 1
L35 "delay.v": \$finish at simulation time 135
81 simulation events

Quote:

> I am learning Verilog. However, I have a
> fair knowledge of VHDL.

> VHDL provides two delay models - inertial
> and transport delay models.

> Verilog does not have the keywords
> "inertial" and "transport".

> What is the delay model used in a
> continuous assignment statement ?

> assign #5 x = a & b;

> If it is the transport delay model,
> how to specify the use of the inertial delay
> model ? If it is the inertial delay model,
> how do we specify the use of the transport
> delay model ?

> It would be helpful if anyone can provide
> the Verilog-equivalent of the following
> VHDL description.

> ===============================================
> entity NAND_gate is
> port (A : in BIT;
>         B : in BIT;
>         Z : out BIT);
> end NAND_gate;

> architecture ARC_transport of NAND_gate is
> begin
>    Z <= A nand B transport after 5 ns;
> end;

> architecture ARC_inertial of NAND_gate is
> begin
>    Z <= A nand B after 5 ns;
> end;
> ================================================

> Sent via Deja.com http://www.*-*-*.com/
> Share what you know. Learn what you don't.

Sent via Deja.com http://www.*-*-*.com/
Share what you know. Learn what you don't.

Tue, 11 Dec 2001 03:00:00 GMT
Inertial and transport delay in Verilog

Quote:

> I am learning Verilog. However, I have a
> fair knowledge of VHDL.

> VHDL provides two delay models - inertial
> and transport delay models.

> Verilog does not have the keywords
> "inertial" and "transport".

> What is the delay model used in a
> continuous assignment statement ?

> assign #5 x = a & b;

> If it is the transport delay model,
> how to specify the use of the inertial delay
> model ? If it is the inertial delay model,
> how do we specify the use of the transport
> delay model ?

Good question.  I was under the impression that the only way to model
inertial and transport delays was by using delayed register data type
assignments within an always procedural block.  This is what I read:

- Inertial delays are modeled with delayed evaluation and blocking
assignments:

#5 sum = a + b;  // Adder with inertial delay

- Transport delays are modeled with delayed assignment and non-blocking
assignments:

out <= #5 in;  // Delay line with transport delay

- Clock-to-Q delays are modeled using delayed assignment and non-blocking
assignments:

q <= #5 d; // Flip-flop with delay

My guess is that the continuous assignment delay is a transport delay.  My
other guess is that there is no such thing as an inertial delay model for
continuous assignments.  But these are just guesses.  What do the experts
say?
--
Marty

Tue, 11 Dec 2001 03:00:00 GMT

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