I am wondering what I am going to do with the following simulation error. 
Author Message
 I am wondering what I am going to do with the following simulation error.

Hi, all:

I am wondering what I am going to do with the following simulation error.

Best Regards,
Leon

--------------------------------------------------->
Compiling source file "tm.v"
Compiling included source file "/home/leonle/gatelevel/stg1_ld_net.v"
Continuing compilation of source file "tm.v"
Scanning library directory "/tools/my_tech_liblog_lib/std_cells"
Scanning library directory "/tools/my_tech_liblog_lib/std_cells"

Error!    Instance specific item not found in `uselib                          
          path:                                                                
          Directory : /tools/my_tech_lib                    
          log_lib/std_cells                                                    
          Libext : .v                                       [Verilog-LISRE]    
          "/tools/my_tech_liblog_lib/std                    
          _cells/dfcrb1.v",...

Error!    Instance specific item not found in `uselib                          
          path:                                                                
          Directory : /tools/my_tech_lib                    
          log_lib/std_cells                                                    
          Libext : .v                                       [Verilog-LISRE]    
          "/tools/my_tech_liblog_lib/std                    
          _cells/dfcrq2.v",...

Error!    Module or primitive (U_FD_P_RB_NO) not defined    [Verilog-MOPND]    
          "/tools/my_tech_liblog_lib/std                    
          _cells/dfcrb1.v", 42: U_FD_P_RB_NO #(1)  (buf_Q,                    
          D, CP, CDN, notifier);

Error!    Module or primitive (U_FD_P_RB_NO) not defined    [Verilog-MOPND]    
          "/tools/my_tech_liblog_lib/std                    
          _cells/dfcrq2.v", 42: U_FD_P_RB_NO #(1)  (Q, D,                      
          CP, CDN, notifier);
4 errors
End of VERILOG-XL 3.10.p001   Apr 27, 2001  09:45:39



Thu, 23 Oct 2003 16:08:01 GMT  
 I am wondering what I am going to do with the following simulation error.
Hi,

 Error!    Module or primitive (U_FD_P_RB_NO) not defined

  This means that there is a UDP (User Defined Primitive) (or a
module, but likely it is an UDP) is UNDEFINED!

Check the file:

 /tools/my_tech_liblog_lib/std_cells/dfcrb1.v

Line number: 42

It should read like:

 U_FD_P_RB_NO #(1) (buf_Q, D, CP, CDN, notifier);

And this "U_FD_P_RB_NO" is something that's not "visible" to the
simulator/compiler.

        Essentially you are not properly giving the required standard cell
libraries to Verilog-XL. Where did you get this library from? In some
cases I have seen that the UDPs are put together in a separate file.
So try and search for them in your library (Verilog library, provided
by your ASIC Vendor).

HTH,
Srini

Quote:

> Hi, all:

> I am wondering what I am going to do with the following simulation
> error.

> Best Regards,
> Leon

--
Srinivasan Venkataramanan (Srini)
ASIC Design Engineer,
Chennai (Madras), India


Fri, 24 Oct 2003 14:50:12 GMT  
 
 [ 2 post ] 

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