OVI LRM Questions 
Author Message
 OVI LRM Questions

I have a couple questions about the LRM (1.0).

1) "real" is not listed as a keyword in appendix F.  Is this a mistake?

2) The Verilog-XL simulator apparently allows ranges to be specified
   in parameter declarations, for example:

     parameter [2:0] foo = 3'b1;

   I can't find anything in the language syntax that allows this.  Is
   this legal?

--
George Lippincott



Sat, 03 Feb 1996 04:48:13 GMT  
 OVI LRM Questions
If Verilog accepts the declarations, and the simulation performs
as expected - it is valid. For Verilog. That version. Does OVI
agree? Maybe. Chronologic VCS? Maybe. This version.

You're always safest whats documented in the language spec.
Just about every piece of software written has some
"back door" anomolies but generally one should stear
clear of these.



Sat, 03 Feb 1996 08:19:39 GMT  
 OVI LRM Questions

George> I have a couple questions about the LRM (1.0).
George> 1) "real" is not listed as a keyword in appendix F.  Is this a mistake?

George> 2) The Verilog-XL simulator apparently allows ranges to be specified
George>    in parameter declarations, for example:
George>      parameter [2:0] foo = 3'b1;

George>    I can't find anything in the language syntax that allows this.  Is
George>    this legal?
George> --
George> George Lippincott

        ``real'' really is a part of the language, although it
is definately in a gray area with respect to mixing with non reals.

        See section 3.10 of your Verilog Hardware Description Language
Reference Manual (LRM) Version 1.0, page 3-18.

        parameters can optionally accept ranges, as noted in section
3.11 of the same manual, on page 3-19. (See the big shadowed box on
the bottom of the page, which says (I quote without permission):

        "Implementation specific detail: Some implementations accept a
range specification on the parameter declaration."

        And, as Brian Balthazor of Amdahl noted,

Brian> If Verilog accepts the declarations, and the simulation performs
Brian> as expected - it is valid. For Verilog. That version. Does OVI
Brian> agree? Maybe. Chronologic VCS? Maybe. This version.

Brian> You're always safest whats documented in the language spec.
Brian> Just about every piece of software written has some
Brian> "back door" anomolies but generally one should stear
Brian> clear of these.

        So, both reals and parameters accepting ranges are documented
in the OVI LRM 1.0.

        Their documentaion survives in the OVI LRM 2.0a, with minor
editorial changes, like noting reals are initialized to zero.

        However, in OVI LRM 2.0a, real still hasn't made it to the
Appendix E, List of key words.  

        OVI, are you listing?

        Chronologic VCS accepts both and fully supports their usage in
accordance with the OVI 1.0 specification, as well as, to the best of
or knowledge, in accordance with Verilog-XL's implementation.

        Amplifing on Brian's point, does your synthesis tool handle
parameters with ranges? (Few synthesis tools would do anything with
reals, which may be how it escaped inclusion in the List of Keywords).

--
Michael T.Y. McNamara                          1+(415) 965-3312
,------.                                       1+(415) 965-2705 FAX

`------'       {yes, company has new logo..  *sigh*}



Sun, 04 Feb 1996 02:01:46 GMT  
 
 [ 3 post ] 

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