VHDL vs. Verilog happened at SNUG not IVC 
Author Message
 VHDL vs. Verilog happened at SNUG not IVC


> One data point which may help shed some light on the mind set of the two
> HDL conference organizers, and why they may not see eye to eye.  The
> contest in question at the Verilog conference was the design of a counter.
> The design contest at a recent VHDL conference was the Denver Airport
> baggage handling system.


Kirk, again I'd like to clarify, this design contest wasn't held at *any*
Verilog conference -- it was held at the Synopsys Users Group Meeting (which
is more of a synthesis oriented conference.)  As I told Fred, if you wish to
catagorize the Synopsys meeting from historical company tastes, this meeting
would perhaps be seen as more VHDL than Verilog biased from a Synopsys, Inc.
point of view because they only sell a VHDL simulator.  How the customers
see it is another story.  

Also, I'd like to stress that this design contest was not crafted to be a
referendum on whether VHDL or Verilog is a better language for serious
hardware designers to use.  The fact that 89% of the Verilog designers
completed while 100% of the VHDL design *didn't* complete it was a surprize
to an awful lot of us!

I know that this may seem like I'm nitpicking; but I just want to try to keep
the facts in this contest straight in the public's mind when this contest is
being discussed.
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Wed, 03 Dec 1997 03:00:00 GMT  
 [ 1 post ] 

 Relevant Pages 

1. VHDL vs. Verilog happened at SNUG not IVC

2. Snug presentation on verification in VHDL and Verilog

3. Snug presentation on verification in VHDL and Verilog

4. Review of SNUG & IVC '95

5. Review of SNUG & IVC '95

6. VHDL vs Verilog

7. Q: Verilog VS VHDL/VITAL for Gate Level Simulation

8. Verilog vs VHDL Syntax comparison


10. verilog vs VHDL

11. verilog vs VHDL

12. Verilog vs VHDL


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