Looking for an Integer Divider model 
Author Message
 Looking for an Integer Divider model

Hello Group,    
I'm in search of a Verilog model or design suggestions of an integer
divider that could be modified to meet the following parameters:

-- 14-bit divisor
-- 28-bit dividend
-- 15-bit quotient
-- dividend will never be less than divisor.
-- number of pipeline steps is open, but requires consistent    number for
any conversion.
-- quotient is only 15-bits  because divisor is never less than  
14'h1000.

I have been able to accomplish this by use of restoring division, but
results are slow and resource requirements are enormous.

My present target is open to any Altera Flex 10k.

Any suggestions are most appreciated.

Regards,
John
OIS Optical Imaging Systems



Sat, 08 Jan 2000 03:00:00 GMT  
 Looking for an Integer Divider model

I designed a srt radix 4 divider. It is the same sort of
technique used in the pentium and many other high performance
processors for doing a division. SRT radix 4 division makes
use  of a lookup table (only ~ 1000 entries) to perform the
division faster... it generates 2 qotient bits per clock cycle.

Each clock cycle is limited in speed by a single ripple carry
in a adder the width of the dividend. Faster implemenations
make use of a larger table and replace the ripple carry adder
with a CSA (carry save adder). This variation on the design
causes the ripple carry prop delay only to be incurred on the
very last cycle of the division, all other cycles can be performed
significantly faster. My version does not use the CSA variation.

if your interested in the design let me know... it has actually
been tested extensively as well against the refereence divides of
the host machine the verilog simulations were run on.

enjoy,
coy

Coy Toavs                                        Email:  

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Sat, 15 Jan 2000 03:00:00 GMT  
 Looking for an Integer Divider model

Hi

I believe our verilog developpers could be interested in this design!
Please can you contact me?

Quote:
> if your interested in the design let me know... it has actually
> been tested extensively as well against the refereence divides of
> the host machine the verilog simulations were run on.



Tue, 25 Jan 2000 03:00:00 GMT  
 
 [ 5 post ] 

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