transport delays - how? 
Author Message
 transport delays - how?

Hej.

How do I model a *transport* delay in verilog?

In VHDL it's like this: my_out <= transport after 5 ns my_input;
but what's the Verilog equivalent?

regards

Magnus S?derberg



Mon, 04 Jun 2001 03:00:00 GMT  
 transport delays - how?

Quote:

> Hej.

> How do I model a *transport* delay in verilog?

> In VHDL it's like this: my_out <= transport after 5 ns my_input;
> but what's the Verilog equivalent?

> regards

> Magnus S?derberg

vhdl has gained from verilog. Verilog supports inertial delay mode. If
you want to
simulate with transport delay mode, you should run verilog with a
special option

    verilog   +transport_path_delays   <your_file.v>

you should be using ver 2.1 or higher.



Tue, 05 Jun 2001 03:00:00 GMT  
 transport delays - how?
Please note that +transport_path_delays enables only transport pin-pin
delays in a specify block, as the option implies.

For RTL transport delays, you have to drive the signal from a register
into which you make Non-Blocking Assigns.

Quote:


> > Hej.

> > How do I model a *transport* delay in verilog?

> > In VHDL it's like this: my_out <= transport after 5 ns my_input;
> > but what's the Verilog equivalent?

> > regards

> > Magnus S?derberg

> vhdl has gained from verilog. Verilog supports inertial delay mode. If
> you want to
> simulate with transport delay mode, you should run verilog with a
> special option

>     verilog   +transport_path_delays   <your_file.v>

> you should be using ver 2.1 or higher.

--
Ashutosh Varma                                           Axis Systems
Senior Application Specialist                          209 Java Drive

Phone: (408)588-2000 x143                          Fax: (408)588-1662


Tue, 05 Jun 2001 03:00:00 GMT  
 transport delays - how?

Quote:

> Hej.

> How do I model a *transport* delay in verilog?

> In VHDL it's like this: my_out <= transport after 5 ns my_input;
> but what's the Verilog equivalent?

Use the non-blocking assignment e.g. my_out <= #5 my_input.
They use transport delays.

buf and continuous assignments use inertial delay
e.g.

buf #(5) (my_out, my_input);
assign #5 my_out = my_input;



Tue, 05 Jun 2001 03:00:00 GMT  
 transport delays - how?

If you want to model transport delay in RTL:

reg delayed_signal;


   delayed_signal <= #5 signal;

Note the use of a non-blocking assignment.  A blocking assignment won't work



Tue, 05 Jun 2001 03:00:00 GMT  
 
 [ 5 post ] 

 Relevant Pages 

1. Transport Delay and Inertial Delay

2. Transport Delay Vs Inertial Delay

3. transport delays

4. transport delay

5. Inertial and transport delay in Verilog

6. Transport delays in verilog

7. Altera AHDL / transport delay

8. Inertial and transport delay in Verilog

9. inertial vs. transport delay

10. transport delays? (or, where did my pulse go?)

11. Transport vs. Inertial....ooops (DELAY item)

12. Transport/Inertial DElay's

 

 
Powered by phpBB® Forum Software