Verilog Module won't instantiate in Xilinx ECS 
Author Message
 Verilog Module won't instantiate in Xilinx ECS

Dear people,

I create a module, for example, a simple adder in Verilog. It synthesises
fine. I then create a schematic symbol from it, but the ".sym" file contains
very little information, and when I place it in to a schematic module in the
project, no symbol appears.

Has anybody else had the same problem? I am using the latest ISE (5.2 with
SP 3) as part of the WebPack.

Regards to all

PETE MASH



Mon, 02 Jan 2006 00:01:05 GMT  
 Verilog Module won't instantiate in Xilinx ECS
Answer found:

It's because the schematic symbol generator doesn't support Verilog 2001

Regards

PETER MASH


Quote:
> Dear people,

> I create a module, for example, a simple adder in Verilog. It synthesises
> fine. I then create a schematic symbol from it, but the ".sym" file
contains
> very little information, and when I place it in to a schematic module in
the
> project, no symbol appears.

> Has anybody else had the same problem? I am using the latest ISE (5.2 with
> SP 3) as part of the WebPack.

> Regards to all

> PETE MASH



Mon, 02 Jan 2006 00:32:24 GMT  
 Verilog Module won't instantiate in Xilinx ECS

Quote:

> Answer found:

> It's because the schematic symbol generator doesn't support Verilog 2001

Out of curiosity, what Verilog-2001 feature were you using?

Since you said it was a simple module, I am guessing ANSI-C-style
module declarations.



Mon, 02 Jan 2006 08:05:56 GMT  
 Verilog Module won't instantiate in Xilinx ECS
Yes,
e.g.

module Adder(in1,in2,out);

input wire [7:0] in1;
input wire [7:0] in2;
output wire [8:0] out;

assign out = in1 + in2;

endmodule



Quote:
> > Answer found:

> > It's because the schematic symbol generator doesn't support Verilog 2001

> Out of curiosity, what Verilog-2001 feature were you using?

> Since you said it was a simple module, I am guessing ANSI-C-style
> module declarations.



Mon, 02 Jan 2006 14:23:51 GMT  
 
 [ 4 post ] 

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