I create a module, for example, a simple adder in Verilog. It synthesises fine. I then create a schematic symbol from it, but the ".sym" file contains very little information, and when I place it in to a schematic module in the project, no symbol appears.
Has anybody else had the same problem? I am using the latest ISE (5.2 with SP 3) as part of the WebPack.
Regards to all
PETE MASH
Mon, 02 Jan 2006 00:01:05 GMT
Peter Mas #2 / 4
Verilog Module won't instantiate in Xilinx ECS
Answer found:
It's because the schematic symbol generator doesn't support Verilog 2001
Regards
PETER MASH
Quote:
> Dear people,
> I create a module, for example, a simple adder in Verilog. It synthesises > fine. I then create a schematic symbol from it, but the ".sym" file contains > very little information, and when I place it in to a schematic module in the > project, no symbol appears.
> Has anybody else had the same problem? I am using the latest ISE (5.2 with > SP 3) as part of the WebPack.
> Regards to all
> PETE MASH
Mon, 02 Jan 2006 00:32:24 GMT
Steven Sha #3 / 4
Verilog Module won't instantiate in Xilinx ECS
Quote:
> Answer found:
> It's because the schematic symbol generator doesn't support Verilog 2001
Out of curiosity, what Verilog-2001 feature were you using?
Since you said it was a simple module, I am guessing ANSI-C-style module declarations.
Verilog Module won't instantiate in Xilinx ECS