Signed / Unsigned question. 
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 Signed / Unsigned question.

Hi.

I try to use negative numbers in a verilog module (It is not
syntesizable).
It works in ModelTech but does not work with Verilog-XL.

My intention is to get a 32 bit vector I_in and assign it to real
variable.
than i divide it and multiply it. Whan i multiply it by (-1) the
Verilog-XL
converts it to 2'nd compliment and then 'forgets' that it is negativ.

How should i work with negative numbers?

Here is my code:

  input up , dn ,hi_clk;
  input [width-1:0] I_in;
   real               I,I_mul_real,x_n,b1,y_n;


      begin
         I_mul_real = I_in;
         I = I_mul_real / 1000;  // Convert nA to uA

         x_n = (up + (-1 * dn)) * I;      <-- Here x_n becomes 2'nd
compliment.
         y_n = x_n * b1;
      end

Thanks
   Doron
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Thu, 20 Sep 2001 04:00:00 GMT  
 Signed / Unsigned question.
Why don't u use "reg" type? Never heard "real" type..

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Mon, 24 Sep 2001 03:00:00 GMT  
 
 [ 2 post ] 

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