Signed/Unsigned Operations for OVI 2.0
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Signed/Unsigned Operations for OVI 2.0

Hello ALL,

If there is an arithmetic operation involving an integer and a register
what would be the type of the operation - signed or unsigned ?

As an example, if we have a

reg [0:15] R;
integer I;

and

an expression like ( R  OP  I )

or

( I  OP  R )

( where OP is +,-,* or / )

will OP be treated as a signed or an unsigned operation ?
We assume that there is no `signed or `unsigned directive specified.

Thanks.

Kousik Mukherjee

Sun, 01 Oct 2000 03:00:00 GMT
Signed/Unsigned Operations for OVI 2.0

Quote:

> Hello ALL,

> If there is an arithmetic operation involving an integer and a register
> what would be the type of the operation - signed or unsigned ?

> As an example, if we have a

>   reg [0:15] R;
>   integer I;

> and

>   an expression like ( R  OP  I )

>                          or

>                      ( I  OP  R )

>   ( where OP is +,-,* or / )

> will OP be treated as a signed or an unsigned operation ?
> We assume that there is no `signed or `unsigned directive specified.

The oft misquoted truism, 'Signedness is in the eye of the beholder'
is appropriate here: what is the context of the expression?

If it is assignment, then the signedness of the destination governs
the result, doesn't it:

I1 = R - I;

'R-I' is calculated using 2's complement arithmetic, and
whether we consider R or I signed or unsigned, the same bit pattern is
produced, and stored into I1, again, with out regard for whether I1 is
declared as a signed (integer) or unsigned (register) storage
location.

The only ways to tell are the display operation, and the
relational operations:

\$display("%d", I1);           // will print the sign

if ( I1 < 0) \$display("less"); // 0xffffffff in an integer is less than 0;
// 0xffffffff in a register is not.

So, consider the following test:

module a;
integer INTA, INTB, INTC;
reg [66:0] REGA, REGB, REGC;

initial begin
INTA = (2*32'h40000000)/2;  // Stmt A
REGA = (2*32'h40000000)/2;  // Stmt B
INTB = (4 - 6 ) * 3'd2;     // Stmt C
REGB = (4 - 6 ) * 3'd2;     // Stmt D
INTC = (4 - 6 ) * 3'd2 / 2; // Stmt E
REGC = (4 - 6 ) * 3'd2 / 2; // Stmt F
#10;
\$display("INTA %d %x",INTA,INTA);
\$display("INTB %d %x",INTB,INTB);
\$display("INTC %d %x",INTC,INTC);
\$display("REGA %d %x",REGA,REGA);
\$display("REGB %d %x",REGB,REGB);
\$display("REGC %d %x",REGC,REGC);
#10;
if ( ((2*32'h40000000)/2) < 2) \$display("less"); else \$display("more");
if ( ((2*32'h40000000)/2) < 2) \$display("less"); else \$display("more");
if ( ((4 - 6 ) * 3'd2) < 2) \$display("less"); else \$display("more");
if ( ((4 - 6 ) * 3'd2) < 2) \$display("less"); else \$display("more");
if ( ((4 - 6 ) * 2) < 2) \$display("less"); else \$display("more");
if ( ((4 - 6 ) * 2) < 2) \$display("less"); else \$display("more");
if ( ((4 - 6 ) * 3'd2 / 2) < 2) \$display("less"); else \$display("more");
if ( ((4 - 6 ) * 3'd2 / 2) < 2) \$display("less"); else \$display("more");

end // initial begin
endmodule // a

You should get:

INTA  1073741824 40000000
INTB          -4 fffffffc
INTC  2147483646 7ffffffe
REGA            1073741824 00000000040000000
REGB 147573952589676412924 7fffffffffffffffc
REGC  73786976294838206462 3fffffffffffffffe
more
more
more
more
less
less
more
more

Form this you can surmise that if anything in an expression is
unsigned, the rest is unsigned.

--

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_\///\/        Formerly Silicon Sorcery
\//\/    Get my verilog emacs mode from
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Sat, 07 Oct 2000 03:00:00 GMT

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