COURSE: High Level Design Using Verilog, Feb 12-16, Beaverton OR 
Author Message
 COURSE: High Level Design Using Verilog, Feb 12-16, Beaverton OR

Qualis Design Corporation will be offering another session of its popular
course, `A Comprehensive Introduction to High Level Design Using Verilog'
in Beaverton, Oregon, during the week of February 12-16.

New for 1996!
-------------
Qualis is teaming-up with Chip Express, the leader in ASIC Time-to-Market
Solutions, in 1996 with technology support in Qualis' High Level Design
courses.  All students who successfully complete a Qualis High Level Design
course will receive a coupon good for 75% off the cost of their first
Chip Express laser gate-array prototypes!  Call us for more details.

A brief overview of our next course follows:

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            A Comprehensive Introduction To High Level Design
                            Using Verilog

            Copyright (c) 1995,1996 Qualis Design Corporation

`A Comprehensive Introduction to High Level Design Using Verilog' is a
fast paced, 5-day hands-on, multimedia course designed not only to
teach High Level Design techniques and the Verilog language, but to
make class participants immediately productive in a system design
environment using state-of-the-art simulation and synthesis tools.

After an introduction to Verilog, the course deviates from the
traditional bottom-up, gates-to-behavi{*filter*}modeling presentation of
other Verilog courses and reverses the flow, teaching top-down design
practices, with early special emphasis on coding for synthesis,
efficient testbench generation and advanced design verification
techniques. These skills are reinforced throughout the week while
teaching Verilog from a top-down perspective.

The course labs are designed to accommodate the learning aptitudes of
a wide range of students with diverse design experiences. Each lab is
structured into three parts:

     1.        Fundamental Concepts Review and Experience
     2.        Recognition of Common Mistakes and Correcting Problems
     3.        Additional Material for Advanced Students

All students complete parts one and two of each lab.  Part three is
for students who finish early and want to learn additional material.
This lab structure caters to all student skill levels and provides
excellent opportunities to expand one's knowledge of Verilog
simulation and synthesis techniques.

Each day of class includes interactive lecture sessions with two to
four labs and written exercises distributed throughout the day.
Students will have access to individual Sun Sparcstations, the Verilog
simulation environment, and the Synopsys DC Expert synthesis
environment for use during the laboratory sessions. The instructor
presents the material using a projection system that allows 30% more
material to be presented in a given amount of time with vivid,
interest-grabbing color slides, as compared to black & white
overheads.

About Qualis Design Corporation
-------------------------------
Founded in 1992, Qualis Design Corporation has quickly become the
leading independent provider of High Level Design consulting and
training services.  The company provides services to leading-edge high
technology firms worldwide, including Intel, Hewlett-Packard,
Tektronix, Xerox, TRW, Northern Telecom and Bell-Northern Research.

Qualis High Level Design Training Courses are conducted on leading-
edge Sun workstations using the latest EDA vendor tools, and are
taught by engineering professionals with extensive digital design
experience.  Engineers who complete the High Level Design With Verilog
course will be more efficient users of system simulation tools, will
be capable of implementing advanced simulation environments, and will
have the knowledge to successfully complete complex design projects.
Engineers with previous exposure to Verilog and VHDL will also benefit
from the leading-edge material presented.

Additional Information
----------------------
The High Level Design Using Verilog course is taught over five
consecutive days.  Complimentary continental breakfast, a full lunch
and afternoon refreshments are provided for each day of the class.
Lodging conveniently located near the class site is available, with
morning and evening shuttle service.

The next regularly scheduled class will be held on:

`A Comprehensive Introduction to High Level Design Using Verilog'

     Class Dates:       February 12 - 16, 1996

     Time:              8:30 AM to 5:00 PM

     Class Location:    Qualis Design Corporation
                        Corporate Headquarters
                        Beaverton, OR

For more information about this course, including course description
and syllabus, contact us at:

                      Qualis Design Corporation
                     15455 NW Greenbrier Parkway
                              Suite 250
                       Beaverton, OR 97006 USA

                        Phone: +1-503-531-0377
                         FAX: +1-503-629-5525

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Copyright (c) 1995,1996 Qualis Design Corporation.  All rights reserved.

`DC Expert' is a trademark of Synopsys, Inc.
`Verilog' is a registered trademark of Cadence Design Systems, Inc.
`The ASIC Time-to-Market Solution' is a trademark of Chip Express Corp.



Sun, 19 Jul 1998 03:00:00 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. COURSE: High Level Design Using Verilog, Dec, Jan, Feb, Beaverton OR

2. COURSE: High Level Design Using Verilog, Dec, Jan, Feb, Beaverton OR

3. COURSE: High Level Design Using Verilog, Dec, Jan, Feb, Beaverton OR

4. COURSE: High Level Design Using VHDL, Feb, Beaverton OR

5. COURSE: High Level Design Using VHDL, Dec, Feb, Beaverton OR

6. COURSE: High Level Design Using VHDL, Dec, Feb, Beaverton OR

7. COURSE: High Level Design Using Verilog, Beaverton, Oregon

8. COURSE: High Level Design Using Verilog, Beaverton, Oregon

9. COURSES: High Level Design Using Verilog, Beaverton, Oregon

10. COURSES: High Level Design Using Verilog, Beaverton, OR

11. COURSE: High Level Design Using Verilog, March 25-29, Beaverton OR

12. COURSE: High Level Design Using Verilog, Nov 6-10, Beaverton OR

 

 
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