verilog, Initial statement problem

Roald Grav
#1 / 5

Initial statement problem

Hi,

I wonder if any of you had this problem with Verilog.
The code below generates the sytax error at line with initial
statement.
I am copying the code from the textbook, and I am very confued!

module clock(clock);

output clock;
reg clock;

initial
clock = 0;

Any help will be greatly appreciated,

Roald.

Wed, 01 May 2002 03:00:00 GMT

Swapnajit Mittr
#2 / 5

Initial statement problem

Quote:

> Hi,

> I wonder if any of you had this problem with Verilog.
> The code below generates the sytax error at line with initial
> statement.
> I am copying the code from the textbook, and I am very confued!

> module clock(clock);

> output clock;
> reg clock;

> initial
> clock = 0;

initial
clock = 1'b0;

always
#my_time_period_divided_by_2 clock = ~clock;
endmodule
--
=-=-= 100% pure Verilog PLI - go, get it ! =-=-=
Principles of Verilog PLI -By- Swapnajit Mittra
Kluwer Academic Publishers. ISBN: 0-7923-8477-6
http://www.angelfire.com/ca/verilog/

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Wed, 01 May 2002 03:00:00 GMT

Edward Arthu
#3 / 5

Initial statement problem

Stupid question, do you have an 'endmodule' statement?

Interesting to see the module and signal name being the
same but my simulator doesn't complain about that.

/Ed

Quote:

> Hi,

> I wonder if any of you had this problem with Verilog.
> The code below generates the sytax error at line with initial
> statement.
> I am copying the code from the textbook, and I am very confued!

> module clock(clock);

> output clock;
> reg clock;

> initial
> clock = 0;

> Any help will be greatly appreciated,

> Roald.

--

Fri, 03 May 2002 03:00:00 GMT

Thit Siriboo
#4 / 5

Initial statement problem

Quote:

> Hi,

> I wonder if any of you had this problem with Verilog.
> The code below generates the sytax error at line with initial
> statement.
> I am copying the code from the textbook, and I am very confued!

> module clock(clock);

> output clock;
> reg clock;

> initial
> clock = 0;

> Any help will be greatly appreciated,

> Roald.

My guess is you try it on a synthesiser and some synthesiser cannnot
synthesise initial.

hope that help
Thit.

Sat, 04 May 2002 03:00:00 GMT

dharmesh_hal..
#5 / 5

Initial statement problem

Hellow brother,
First of all there is one small bug in your module. You forgot
endmodule.Let me know what you want to do? you want to synthesize it or
you want to simulate it.Let me tell you one thing initial is not
synthesizable but you can simulate it.
Dear, whenever you will write code, start thinking what
hardware it will make.If you will do this practice, you will never ask
this type of silly question.
Contact me regarding any type of verilog question.

Quote:

> Hi,

> I wonder if any of you had this problem with Verilog.
> The code below generates the sytax error at line with initial
> statement.
> I am copying the code from the textbook, and I am very confued!

> module clock(clock);

> output clock;
> reg clock;

> initial
> clock = 0;

> Any help will be greatly appreciated,

> Roald.

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Before you buy.

Sun, 05 May 2002 03:00:00 GMT