Mixed VHDL/Verilog simulator ? 
Author Message
 Mixed VHDL/Verilog simulator ?

Hi all
We are planning to buy an HDL simulator. We use VHDL but we've found a
very interesting design that's written in Verilog (and doesn't exist in
VHDL). This would also allow us to use Verilog IP.
What tools do you know that can co-simulate VHDL and Verilog? Does
Active-HDL do that? (I know ModelSim does...)

Coming back from reading comp.lang.vhdl FAQ, I see that Smash (Dolphin
Integration) also does it...
What would you recommend?

Thanks in advance
Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel +33 1 46 67 51 11      92400 COURBEVOIE
Fax +33 1 46 67 51 01      FRANCE

Fri, 01 Nov 2002 03:00:00 GMT  
 [ 1 post ] 

 Relevant Pages 

1. Mixed VHDL/Verilog simulator ?

2. Re : Verilog / VHDL mixed simulators

3. Verilog / VHDL translator or mixed simulator

4. Verilog / VHDL translator or mixed simulator

5. Translator Verilog->VHDL and VHDL simulator

6. mixed mode simulators (VHDL with other gate level models)

7. Mixed VHDL and Verilog with Xilinx ISE

8. problems for design using mixed verilog and vhdl

9. Aldec VHDL/Verilog Simulator !

10. Mixed VHDL and Verilog Design Question

11. ncverilog and mixed vhdl-verilog simulation

12. European Verilog/VHDL simulator vendors


Powered by phpBB® Forum Software