A problem with interfacing with UART 16550 
Author Message
 A problem with interfacing with UART 16550

Hi all,
    We are trying to design the I/O for a microprocessor we are
designing this term.
    The processor has a 3 pipeline architecture with clock cycle of 16
ns. We were exploring the possibility of using UART PC16550D (
http://www.*-*-*.com/ ) for this. However, we
found that the write and read operations for the UART are much much
slower than the system clock (on the order of 50 ns - 100 ns). This is a
stumbling block. Any suggestions would be welcome.
    Not sure if this is the right NG to post this question, but it came
close.

Thanks in advance !!

Madhusudan Singh.



Fri, 19 Sep 2003 12:09:19 GMT  
 A problem with interfacing with UART 16550

Quote:

> Hi all,
>     We are trying to design the I/O for a microprocessor we are
> designing this term.
>     The processor has a 3 pipeline architecture with clock cycle of 16
> ns. We were exploring the possibility of using UART PC16550D (
> http://www.radiometrix.co.uk/dsheets/uart.pdf ) for this. However, we
> found that the write and read operations for the UART are much much
> slower than the system clock (on the order of 50 ns - 100 ns). This is a
> stumbling block. Any suggestions would be welcome.
>     Not sure if this is the right NG to post this question, but it came
> close.

I would suggest using a asynchronous FIFO to access the UART. You can
read or write from whithin the processor at full speed. But there is
some communication necessary to ensure proper opperation. And a DMA
access would be nice, too.

For the clock generation of the external UART clock just use a clock
divider or a modulo(2^n) counter and add an approriate value. The MSB
is the output then.

BTW do you really need a full UART? It is no problem to build a UART
compatible interface, which implements just the most common modes in
a FPGA.

--
Chris



Sat, 20 Sep 2003 05:58:16 GMT  
 A problem with interfacing with UART 16550
Madhusudan:
    this is a very classic interfacing problem.
The solution is just as classic:
    most microprocessors have a "wait" input line, which allows to
strech the read or write cycle beyond one clock period. If the processor
wait input is asserted the processor will keep its I/O lines ( R/W,
Adresses etc...) until the wait line is deasserted. All you need is some
logic to count the number of clocks you need.
A newer but somewhat equivalent way to do things, usually on SOC (system
on chip), is to have some dedicated registers which are written at
initialization and somewhat do the same thing, for a chip select
(address range).
By the way: it is unusual to have UART bus access which cannot support
some pretty fast clocks, but this is beyond the point.
I hope this helped.
        Andre Gompel.
Quote:

> Hi all,
>     We are trying to design the I/O for a microprocessor we are
> designing this term.
>     The processor has a 3 pipeline architecture with clock cycle of 16
> ns. We were exploring the possibility of using UART PC16550D (
> http://www.radiometrix.co.uk/dsheets/uart.pdf ) for this. However, we
> found that the write and read operations for the UART are much much
> slower than the system clock (on the order of 50 ns - 100 ns). This is a
> stumbling block. Any suggestions would be welcome.
>     Not sure if this is the right NG to post this question, but it came
> close.

> Thanks in advance !!

> Madhusudan Singh.



Sat, 18 Oct 2003 10:02:12 GMT  
 
 [ 3 post ] 

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