FPGA Express and ifdef ? 
Author Message
 FPGA Express and ifdef ?

Hello all
I am new to Verilog (but not to logic design)
It seems that FPGA Express doesn't understand the `ifdef directive.
I get lots of error messages (always the same, in fact):
Dpm :Error: Undefined macro `ifdef at or near token '`ifdef'

What's the matter ? (I couldn't find anything about 'ifdef in the help
files)
--
Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel +33 1 46 67 51 11      92400 COURBEVOIE
Fax +33 1 46 67 51 01      FRANCE



Fri, 08 Nov 2002 03:00:00 GMT  
 FPGA Express and ifdef ?
FPGA Express does not include a Verilog pre-processor (unlike the
full Design Compiler product).  `ifdef is a preprocessor directive that
the simulator understands, but not the compiler.  Other compilers such
as Synplicity do support these directives.

If you need to have the `ifdef directives for some reason, consider
using // synopsys translate_off and // synopsys translate_on directives
also.



Fri, 08 Nov 2002 03:00:00 GMT  
 FPGA Express and ifdef ?
Latest version of FPGA Express (v3.3.x or v3.4) can recognize `ifdef,


Quote:
> Hello all
> I am new to Verilog (but not to logic design)
> It seems that FPGA Express doesn't understand the `ifdef directive.
> I get lots of error messages (always the same, in fact):
> Dpm :Error: Undefined macro `ifdef at or near token '`ifdef'

> What's the matter ? (I couldn't find anything about 'ifdef in the help
> files)
> --
> Nicolas MATRINGE           DotCom S.A.
> Conception electronique    16 rue du Moulin des Bruyeres
> Tel +33 1 46 67 51 11      92400 COURBEVOIE
> Fax +33 1 46 67 51 01      FRANCE



Sat, 09 Nov 2002 03:00:00 GMT  
 FPGA Express and ifdef ?
check next menu
   Synthesis -> Options -> Project -> Enable Verilog Pre-processor


Sat, 09 Nov 2002 03:00:00 GMT  
 FPGA Express and ifdef ?

Quote:

> Latest version of FPGA Express (v3.3.x or v3.4) can recognize `ifdef,

  Yes. Old versions of Synopsys FPGA Express does
  not support `ifdef, but newer versions do. This
  probably because you are using an old Xilinx tool?

  Utku

--
I feel better than James Brown.



Sat, 09 Nov 2002 03:00:00 GMT  
 FPGA Express and ifdef ?
^^? O' a crit :

Quote:

> check next menu
>    Synthesis -> Options -> Project -> Enable Verilog Pre-processor

Right, I hadn't even thought it could be disabled.
Thanks a lot
--
Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel +33 1 46 67 51 11      92400 COURBEVOIE
Fax +33 1 46 67 51 01      FRANCE


Sat, 09 Nov 2002 03:00:00 GMT  
 FPGA Express and ifdef ?
You might also try getting hold of Icarus Verilog (www.icarus.com) and
just use
the pre-processor portion of it to filter the code before you pass it to
synplicity.

Icarus verilog is a GPL'd work - which is still under heavy development,
but
this part of the pre-processor works just fine.

Steve Wilson

Quote:

> FPGA Express does not include a Verilog pre-processor (unlike the
> full Design Compiler product).  `ifdef is a preprocessor directive that
> the simulator understands, but not the compiler.  Other compilers such
> as Synplicity do support these directives.

> If you need to have the `ifdef directives for some reason, consider
> using // synopsys translate_off and // synopsys translate_on directives
> also.



Sat, 09 Nov 2002 03:00:00 GMT  
 
 [ 7 post ] 

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