GENERATE statement in verilog 
Author Message
 GENERATE statement in verilog

Hi,

        I'm just convertiing some VHDL to verilog (I know,
nothing better to do). I've not had to deal with the VHDL
GENERATE statement before. What do you think is the best way
to handle this? A conditional compile? In my cases, the
conditional is a static variable which is selected per
instantion of the overall block.

[\] Robert Wood  

The St. Lawrence river - fresh, warm, visible diving.




Mon, 11 Feb 2002 03:00:00 GMT  
 GENERATE statement in verilog
On Thu, 26 Aug 1999 19:19:27 GMT, in comp.lang.vhdl Robert Wood

Quote:
>    I'm just convertiing some VHDL to verilog (I know, nothing
> better to do). I've not had to deal with the VHDL GENERATE statement
> before. What do you think is the best way to handle this? A
> conditional compile? In my cases, the conditional is a static
> variable which is selected per instantion of the overall block.

Sounds like you want to emulate an if generate.  The if generate
provides conditional elaboration.  Conditional compilation is probably
close enough.

For a for generate (providing iterative elaboration), there's nothing
close in verilog.  Probably a macro preprocessor is the way to go.

Paul

--

Cadence Design Systems | www.orcad.com   | spread fear, uncertainty and
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Durham, NC  27722-1767 | 919-479-1671[f] |  --Don Jones, MS's Y2K Product Mgr



Mon, 11 Feb 2002 03:00:00 GMT  
 GENERATE statement in verilog
See this link:

http://www.europa.com/~celiac/tools.html

for Verilog pre-processors...

/Ed

Quote:

> Hi,

>         I'm just convertiing some VHDL to verilog (I know,
> nothing better to do). I've not had to deal with the VHDL
> GENERATE statement before. What do you think is the best way
> to handle this? A conditional compile? In my cases, the
> conditional is a static variable which is selected per
> instantion of the overall block.

--



Mon, 11 Feb 2002 03:00:00 GMT  
 GENERATE statement in verilog

If you are familiar with Perl,  check out Text::EP3 and Text::EP3::Verilog
on CPAN. This is a perl pre-processor with a verilog extension that allows
you to embed perl (and thus generates) directly in your code (among other
things)

Cheers
Gary Spivey


Quote:
> Hi,

> I'm just convertiing some VHDL to verilog (I know,
> nothing better to do). I've not had to deal with the VHDL
> GENERATE statement before. What do you think is the best way
> to handle this? A conditional compile? In my cases, the
> conditional is a static variable which is selected per
> instantion of the overall block.

> [\] Robert Wood

> The St. Lawrence river - fresh, warm, visible diving.





Mon, 11 Feb 2002 03:00:00 GMT  
 GENERATE statement in verilog

Quote:

> If you are familiar with Perl,  check out Text::EP3 and Text::EP3::Verilog
> on CPAN. This is a perl pre-processor with a verilog extension that allows
> you to embed perl (and thus generates) directly in your code (among other
> things)

> Cheers
> Gary Spivey



> > Hi,

> > I'm just convertiing some VHDL to verilog (I know,
> > nothing better to do). I've not had to deal with the VHDL
> > GENERATE statement before. What do you think is the best way
> > to handle this? A conditional compile? In my cases, the
> > conditional is a static variable which is selected per
> > instantion of the overall block.

> > [\] Robert Wood

> > The St. Lawrence river - fresh, warm, visible diving.



Or wait for Verilog-99. I think that this is one of the accepted changes
although waiting for real implementations will probably = watching grass
grow.


Tue, 05 Mar 2002 03:00:00 GMT  
 
 [ 5 post ] 

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