Verilog/VHDL models for VME 
Author Message
 Verilog/VHDL models for VME

Hi,
I'm looking for VME bus models written in Verilog/VHDL at
behavioral/structural level. ...Also looking for models to interface
between the 68000 and the VME bus. Any suggestions will be appreciated.

Thanks,
Arjinder Virdi
___________________________________________________________________
Arjinder Virdi                           Tel:   619-618-2878    
Cadence Spectrum Design                  Fax:   619-618-1460

San Diego, CA 92128                       http://www.*-*-*.com/
___________________________________________________________________



Fri, 30 Jun 2000 03:00:00 GMT  
 
 [ 1 post ] 

 Relevant Pages 

1. vhdl vme bus model ?

2. VHDL model for VME Slave Interface

3. VHDL model for VME-interface

4. c model convert to verilog/VHDl model

5. Memory Models for VHDL/Verilog

6. Vhdl/verilog model for flash memories

7. Verilog model of Xilinx macro in VHDL Testbench fails

8. Verilog or VHDL behavioral models for microprocessors

9. Look for 8051 VHDL/Verilog models

10. VHDL/Verilog Models/Megacells/Performance Tools

11. VHDL/Verilog models for memory (SRAM and DRAM)

12. Translating VHDL into a Verilog model

 

 
Powered by phpBB® Forum Software