In Need of High Level ASIC Design Engineers-- Please Read 
Author Message
 In Need of High Level ASIC Design Engineers-- Please Read

    New Millennium Inc., a leading supplier of Software consultants and
IT
professionals to clients across the U.S. and around the world, has the
following contract positions available with an immediate start date.  If

you are interested in this assignment, I can be reached at the numbers
below to discuss this
opportunity in greater detail. The successful candidate must be a U.S.
citizen or hold an active work visa for the U.S.

Location:  MN
Duration: 6-9 months
Description: Looking for 8 ASIC Designers that will be responsible for
designing
 a 150 thousand gate ASIC for a Fibre Channel
Hard Disk Controller. Should have experience with both Synopsis and
Verilog
Design tools with Test Compiler Tool experience.
Will be going from the architectural stage through the deliverable.
Needs full
cycle ASIC development including Static timing,
synthesis and floor layout. Will be working in a team of 4 that will
grow to 12
in a casual work environment.

Location: Los Angeles, CA
Duration: 6-9 months
Description: Will be responsible for taking a piece of hardware from
conception
through delivery. Will take an empty box, get the
system requirements, spec out the layout including specifying the ASIC
(Size and
 Gates) and interface closely with the end client to
bring the unit to delivery. The product is a piece of
Encryption/Decryption
equipment for the Space industry.  Requirements:  2+ years
High Speed Digital Design experience. 6+ Month's Encryption or
Cryptology
experience. Able to get a Secret Clearance

Location: Cedar Rapids, IA
Duration: 6-9 months
Description: Responsible for providing technical leadership in the area
of ASIC
design to engineering teams responsible for the design
of high performance portable radio data products. Accountable for
innovative
solutions to meet stringent quality, cost, and functional goals.
Utilizing leading edge technologies and processes. Provide ASIC design
expertise
 to a team of engineers in the conceptualization,
prototyping, development, and testing of complex radio data products.
Specification, design, and implementation of high performance,
low power, ASIC (150,000 Gates) designs and their associated high speed
microprocessor based circuitry utilizing industry leading
CAE tools (Mentor, VHDL, Synopsys, SPW, etc), for circuit development
and
simulation. Understanding and coordination of a CAD/CAE
equipment needs and purchases. Ensure adherence to Intermec's design
theologies
in the area of Product Development Procedures
(PDP). Drive the concept of concurrent engineering throughout the
project team
to ensure the quality, testability, manufacturability, and
serviceability goals of the design are met. Provide innovative design
approaches
 to exceed customer functionality expectations.
Integration of ASIC designs into, and simulation of, data communications

circuitry involving; high frequency radio components,
custom ASICs, Digital Signal Processors, high speed I/O, and custom
microprocessor architectures.
Requirements:  Solid business skills. In-depth understanding of business

issues.
 MSEE with 3 to 5 years experience or BSEE with 5 to
7 years experience in ASIC design experience. Thorough technical theory
in
communication systems and radio design. Solid analytical
skills in design and problem solving. Excellent verbal, written, and
negotiation
 skills. Ability to work effectively in a concurrent engineering
team environment. Excellent leadership skills. High commitment to
quality and
technical innovation .

Location: Lexington, MA
Duration: 6-9 months
Description: Will be responsible for performing Asic verification for
networking
 products. The chips are for network protocols such as ATM,
Sonet and Routers (over 1 terabit in size)
Requirements:  2+ years Asic design or verification. 3+ years C coding,
2+ years
 Verilog. 2+ years with one or more of the following: ATM,
Sonet, Routers.

Location: Newton, MA
Duration: 6-9 months
Description: Searching for 2 Asic Designers and 3 Asic Verification
consultants
to work as a team in the following project: Client company
is a custom telecomm product development and technology licensing firm;
innovators in Sonet/SDH, ATM, Ethernet & MPEG-2. This
project is to develop a complete protocol-independent Sonet/ATM gigabit
ethernet
 switch (QC-3/12/48) which does Sonet/ATM gigabit
ethernet adaptiation and next generation ICZs for 10 gb layer 3
switching on
Terabit protocol processing chip project (CMOS, 622 Mb
to the pin). Environment: chips are IM gates, VHDL, Verilog, Synopsis,
Synplicity. Testing tools: verification Affirma NC functional simulator,

Synopsys PtimeTime, Mentor Fastscan for ATPG.
Requirements:  2+ years Asic design or verification experience. 1+ year
of the
following UHDL, Synopsis or Verilog (UHDL & Synopsis
preferred).

Location: Freemont, CA
Duration: 3-6 months
Description: Position will involve the integration of large (20 million
transmission, 5 million gate) chips. Will be responsible for clock
distribution,

timing analysis and chip verification. Should have experience
integrating high
speed, complex graphics or 3-D chips. Team environment
(4-6 people).
Requirements:  Must have experience with the following: clock
distribution,
timing analysis, chip verification, and large chip integration.

Thanks for taking the time to review these positions. I look forward to
your
response.

Best regards.

--
Rich Glacken
New Millennium Inc.
phone: 800-381-9507 ext.313
fax: 800-381-8708



Tue, 23 Apr 2002 03:00:00 GMT  
 In Need of High Level ASIC Design Engineers-- Please Read
hi,

I'm very much interested to apply for requirement in Lexington, MA as a
2+ years experienced person, having worked in mentioned fields.

I have worked in ATM/SONET from July 97 to March 99. I have worked in
VHDL, used ModelTech Vsystem and Synopsys to some extent.

Then I shifted place and company. From April 99 onwards I'm working in
Gigabit Ethernet switch/router chip verification. I'm now working in
Verilog, Verilog simulator.

I would be glad if you find myself to be satisfying your requirement.

regards
suresh



Quote:
> Location: Lexington, MA
> Duration: 6-9 months
> Description: Will be responsible for performing Asic verification for
> networking
>  products. The chips are for network protocols such as ATM,
> Sonet and Routers (over 1 terabit in size)
> Requirements:  2+ years Asic design or verification. 3+ years C
coding,
> 2+ years
>  Verilog. 2+ years with one or more of the following: ATM,
> Sonet, Routers.

> Location: Newton, MA
> Duration: 6-9 months
> Description: Searching for 2 Asic Designers and 3 Asic Verification
> consultants
> to work as a team in the following project: Client company
> is a custom telecomm product development and technology licensing
firm;
> innovators in Sonet/SDH, ATM, Ethernet & MPEG-2. This
> project is to develop a complete protocol-independent Sonet/ATM
gigabit
> ethernet
>  switch (QC-3/12/48) which does Sonet/ATM gigabit
> ethernet adaptiation and next generation ICZs for 10 gb layer 3
> switching on
> Terabit protocol processing chip project (CMOS, 622 Mb
> to the pin). Environment: chips are IM gates, VHDL, Verilog, Synopsis,
> Synplicity. Testing tools: verification Affirma NC functional
simulator,

> Synopsys PtimeTime, Mentor Fastscan for ATPG.
> Requirements:  2+ years Asic design or verification experience. 1+
year
> of the
> following UHDL, Synopsis or Verilog (UHDL & Synopsis
> preferred).

> Location: Freemont, CA
> Duration: 3-6 months
> Description: Position will involve the integration of large (20
million
> transmission, 5 million gate) chips. Will be responsible for clock
> distribution,

> timing analysis and chip verification. Should have experience
> integrating high
> speed, complex graphics or 3-D chips. Team environment
> (4-6 people).
> Requirements:  Must have experience with the following: clock
> distribution,
> timing analysis, chip verification, and large chip integration.

> Thanks for taking the time to review these positions. I look forward
to
> your
> response.

> Best regards.

> --
> Rich Glacken
> New Millennium Inc.
> phone: 800-381-9507 ext.313
> fax: 800-381-8708

> --------------4CC2C6437FD3D0BA69C81D91
> Content-Type: text/html; charset=us-ascii
> Content-Transfer-Encoding: 7bit

> <HTML>
> &nbsp;&nbsp;&nbsp; New Millennium Inc., a leading supplier of Software
> consultants and IT
> <BR>professionals to clients across the U.S. and around the world, has
> the
> <BR>following contract positions available with an immediate start
date.&nbsp;
> If
> <BR>you are interested in this assignment, I can be reached at the
numbers
> <BR>below to discuss this
> <BR>opportunity in greater detail. The successful candidate must be a
U.S.
> <BR>citizen or hold an active work visa for the U.S.
> <CENTER>&nbsp;</CENTER>

> <P>Location:&nbsp; MN
> <BR>Duration: 6-9 months
> <BR>Description: Looking for 8 ASIC Designers that will be responsible
> for
> <BR>designing
> <BR>&nbsp;a 150 thousand gate ASIC for a Fibre Channel
> <BR>Hard Disk Controller. Should have experience with both Synopsis
and
> <BR>Verilog
> <BR>Design tools with Test Compiler Tool experience.
> <BR>Will be going from the architectural stage through the
deliverable.
> <BR>Needs full
> <BR>cycle ASIC development including Static timing,
> <BR>synthesis and floor layout. Will be working in a team of 4 that
will
> <BR>grow to 12
> <BR>in a casual work environment.

> <P>Location: Los Angeles, CA
> <BR>Duration: 6-9 months
> <BR>Description: Will be responsible for taking a piece of hardware
from
> <BR>conception
> <BR>through delivery. Will take an empty box, get the
> <BR>system requirements, spec out the layout including specifying the
ASIC
> <BR>(Size and
> <BR>&nbsp;Gates) and interface closely with the end client to
> <BR>bring the unit to delivery. The product is a piece of
> <BR>Encryption/Decryption
> <BR>equipment for the Space industry.&nbsp; Requirements:&nbsp; 2+
years
> <BR>High Speed Digital Design experience. 6+ Month's Encryption or
> <BR>Cryptology
> <BR>experience. Able to get a Secret Clearance

> <P>Location: Cedar Rapids, IA
> <BR>Duration: 6-9 months
> <BR>Description: Responsible for providing technical leadership in the
> area
> <BR>of ASIC
> <BR>design to engineering teams responsible for the design
> <BR>of high performance portable radio data products. Accountable for
> <BR>innovative
> <BR>solutions to meet stringent quality, cost, and functional goals.
> <BR>Utilizing leading edge technologies and processes. Provide ASIC
design
> <BR>expertise
> <BR>&nbsp;to a team of engineers in the conceptualization,
> <BR>prototyping, development, and testing of complex radio data
products.
> <BR>Specification, design, and implementation of high performance,
> <BR>low power, ASIC (150,000 Gates) designs and their associated high
speed
> <BR>microprocessor based circuitry utilizing industry leading
> <BR>CAE tools (Mentor, VHDL, Synopsys, SPW, etc), for circuit
development
> <BR>and
> <BR>simulation. Understanding and coordination of a CAD/CAE
> <BR>equipment needs and purchases. Ensure adherence to Intermec's
design
> <BR>theologies
> <BR>in the area of Product Development Procedures
> <BR>(PDP). Drive the concept of concurrent engineering throughout the
> <BR>project team
> <BR>to ensure the quality, testability, manufacturability, and
> <BR>serviceability goals of the design are met. Provide innovative
design
> <BR>approaches
> <BR>&nbsp;to exceed customer functionality expectations.
> <BR>Integration of ASIC designs into, and simulation of, data
communications

> <P>circuitry involving; high frequency radio components,
> <BR>custom ASICs, Digital Signal Processors, high speed I/O, and
custom
> <BR>microprocessor architectures.
> <BR>Requirements:&nbsp; Solid business skills. In-depth understanding
of
> business
> <BR>issues.
> <BR>&nbsp;MSEE with 3 to 5 years experience or BSEE with 5 to
> <BR>7 years experience in ASIC design experience. Thorough technical
theory
> <BR>in
> <BR>communication systems and radio design. Solid analytical
> <BR>skills in design and problem solving. Excellent verbal, written,
and
> <BR>negotiation
> <BR>&nbsp;skills. Ability to work effectively in a concurrent
engineering
> <BR>team environment. Excellent leadership skills. High commitment to
> <BR>quality and
> <BR>technical innovation .

> <P>Location: Lexington, MA
> <BR>Duration: 6-9 months
> <BR>Description: Will be responsible for performing Asic verification
for
> <BR>networking
> <BR>&nbsp;products. The chips are for network protocols such as ATM,
> <BR>Sonet and Routers (over 1 terabit in size)
> <BR>Requirements:&nbsp; 2+ years Asic design or verification. 3+ years
> C coding,
> <BR>2+ years
> <BR>&nbsp;Verilog. 2+ years with one or more of the following: ATM,
> <BR>Sonet, Routers.

> <P>Location: Newton, MA
> <BR>Duration: 6-9 months
> <BR>Description: Searching for 2 Asic Designers and 3 Asic
Verification
> <BR>consultants
> <BR>to work as a team in the following project: Client company
> <BR>is a custom telecomm product development and technology licensing
firm;
> <BR>innovators in Sonet/SDH, ATM, Ethernet &amp; MPEG-2. This
> <BR>project is to develop a complete protocol-independent Sonet/ATM
gigabit
> <BR>ethernet
> <BR>&nbsp;switch (QC-3/12/48) which does Sonet/ATM gigabit
> <BR>ethernet adaptiation and next generation ICZs for 10 gb layer 3
> <BR>switching on
> <BR>Terabit protocol processing chip project (CMOS, 622 Mb
> <BR>to the pin). Environment: chips are IM gates, VHDL, Verilog,
Synopsis,
> <BR>Synplicity. Testing tools: verification Affirma NC functional
simulator,

> <P>Synopsys PtimeTime, Mentor Fastscan for ATPG.
> <BR>Requirements:&nbsp; 2+ years Asic design or verification
experience.
> 1+ year
> <BR>of the
> <BR>following UHDL, Synopsis or Verilog (UHDL &amp; Synopsis
> <BR>preferred).

> <P>Location: Freemont, CA
> <BR>Duration: 3-6 months
> <BR>Description: Position will involve the integration of large (20
million
> <BR>transmission, 5 million gate) chips. Will be responsible for clock
> <BR>distribution,

> <P>timing analysis and chip verification. Should have experience
> <BR>integrating high
> <BR>speed, complex graphics or 3-D chips. Team environment
> <BR>(4-6 people).
> <BR>Requirements:&nbsp; Must have experience with the following: clock
> <BR>distribution,
> <BR>timing analysis, chip verification, and large chip integration.

> <P>Thanks for taking the time to review these positions. I look
forward
> to
> <BR>your
> <BR>response.

> <P>Best regards.
> <BR>&nbsp;
> <BR>&nbsp;

> <P>--
> <BR>Rich Glacken
> <BR>New Millennium Inc.
> <BR>phone: 800-381-9507 ext.313
> <BR>fax: 800-381-8708

> <BR>&nbsp;</HTML>

> --------------4CC2C6437FD3D0BA69C81D91--

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Sun, 28 Apr 2002 03:00:00 GMT  
 
 [ 2 post ] 

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