difference between case and if statements 
Author Message
 difference between case and if statements

Hi,

I want to know whats the difference between the "case", "casex",
"casez" and its counterpart "if" conditional statement, in their
execution. which realizes priority logic among those? i want to know
at what circumstances a "case" statement synthesis to single level
logic and at what cases "if" statement synthesizes to multilevel
logic?



Sun, 11 Jul 2004 01:20:30 GMT  
 difference between case and if statements

Quote:
> Hi,

> I want to know whats the difference between the "case", "casex",
> "casez" and its counterpart "if" conditional statement, in their
> execution. which realizes priority logic among those? i want to know
> at what circumstances a "case" statement synthesis to single level
> logic and at what cases "if" statement synthesizes to multilevel
> logic?

Hi,

It is very hard to explain through mail, with few lines.

Refer, "A Guide to Digital Design and Synthesis" by Samir Palnitkar.

Regards,
Muthu.



Sun, 11 Jul 2004 21:19:04 GMT  
 difference between case and if statements

Quote:


> > Hi,

> > I want to know whats the difference between the "case", "casex",
> > "casez" and its counterpart "if" conditional statement, in their
> > execution. which realizes priority logic among those? i want to know
> > at what circumstances a "case" statement synthesis to single level
> > logic and at what cases "if" statement synthesizes to multilevel
> > logic?

> Hi,

> It is very hard to explain through mail, with few lines.

> Refer, "A Guide to Digital Design and Synthesis" by Samir Palnitkar.

> Regards,
> Muthu.

Hi,
    The usage of if statements realizes to a priority encoded logic.
Case statements will realize to a Multiplexer.
Regards
Dinesh


Sat, 17 Jul 2004 22:54:20 GMT  
 difference between case and if statements


Quote:
>    The usage of if statements realizes to a priority encoded logic.
>Case statements will realize to a Multiplexer.

Whoa, not so fast!

In VHDL, what you say is (almost) reliably true, except that
some straightforward "if" statements will be implemented
as multiplexers by a sufficiently smart synthesis tool.

In Verilog, case statements have all manner of what you might
politely refer to as "flexibility" and the consequence is that
your statement is simply not true in the general case;
although it is easy enough to write a case statement that
WILL synthesise to a multiplexer, if you are careful.

As someone else said, it's not a question with a five-line answer.
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom

Fax: +44 1425 471573                             Web: http://www.doulos.com

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Sun, 18 Jul 2004 00:53:45 GMT  
 difference between case and if statements

Quote:
>    The usage of if statements realizes to a priority encoded logic.
>Case statements will realize to a Multiplexer.

The case statement may infer priority in Verilog, unless the parallel_case
attribute is used.
---------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  

Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------


Sun, 18 Jul 2004 01:08:57 GMT  
 difference between case and if statements

Quote:

>     The usage of if statements realizes to a priority encoded logic.
> Case statements will realize to a Multiplexer.

Simply not true. You can code (non-)priority logic with both statements.

For a basic intro visit:
http://mufasa.ra.informatik.uni-mannheim.de/lsra/persons/lars/verilog...

Lars
--
Address:  University of Mannheim; D7, 3-4; 68159 Mannheim, Germany
Tel:      +(49) 621 181-2716, Fax: -2713

Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/



Sun, 18 Jul 2004 16:00:50 GMT  
 difference between case and if statements

Quote:

> In Verilog, case statements have all manner of what you might
> politely refer to as "flexibility" and the consequence is that

Do i hear any critics here? You're VHDL guy, right? <grin>

Quote:
> As someone else said, it's not a question with a five-line answer.

Hmm, well, lemme try.
"If you have overlapping conditions, you will end up with priority
 logic using if/case statements. If your conditions are mutually
 exclusive, you'll get parallel logic."

Hey, 3 lines!
Ok, one could say more, but basically it comes down to this.

Lars
--
Address:  University of Mannheim; D7, 3-4; 68159 Mannheim, Germany
Tel:      +(49) 621 181-2716, Fax: -2713

Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/



Sun, 18 Jul 2004 16:05:03 GMT  
 difference between case and if statements

Quote:

> The case statement may infer priority in Verilog, unless the parallel_case
> attribute is used.

Gee, another VHDL'er mixing up c.l.v. ;-)

Now a 2 liner:
"You'll never need full/parallel case pragmas, at least in one case:
 one-hot logic. And even then you could get around. So don't use them!"

Lars
--
Address:  University of Mannheim; D7, 3-4; 68159 Mannheim, Germany
Tel:      +(49) 621 181-2716, Fax: -2713

Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/



Sun, 18 Jul 2004 16:09:14 GMT  
 difference between case and if statements

Quote:

>> The case statement may infer priority in Verilog, unless the parallel_case
>> attribute is used.

>Gee, another VHDL'er mixing up c.l.v. ;-)

>Now a 2 liner:
>"You'll never need full/parallel case pragmas, at least in one case:
> one-hot logic. And even then you could get around. So don't use them!"

>Lars

From IEEE P1364.1 /D1.9 Draft Standard for Verilog ? Register Transfer Level
Synthesis
"Note:The parallel_case attribute directs the synthesis tool to test each and
very case item in the case statement very time the case statement is
xecuted.This attribute causes the synthesis tool to remove any priority that
might be assigned to the case statement
by testing very case item,ven if more than one case item matches the case
xpression.This behavior differs from the behavior of standard Verilog
simulation.

Note:The parallel_case attribute is commonly used to remove priority encoders
from the gate-level implementation of an RTL case statement.Unfortunately,the
RTL case statement may still simulate like a priority encoder,causing a
mismatch between pre-synthesis and post-synthesis simulations.

Note:Adding a default statement to a case statement does not nullifies the
effect of the parallel_case attribute."

Thus, I disagree with your statement ""You'll never need full/parallel case
pragmas, at least in one case:  one-hot logic. And even then you could get
around. So don't use them!"

---------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  

Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------



Mon, 19 Jul 2004 02:47:27 GMT  
 difference between case and if statements

Quote:

> Note:The parallel_case attribute is commonly used to remove priority encoders
> from the gate-level implementation of an RTL case statement.Unfortunately,the
> RTL case statement may still simulate like a priority encoder,causing a
> mismatch between pre-synthesis and post-synthesis simulations.

I find this description somehow confusing. They are saying you get mismatches,
which is true. That should be a reason to not use it, right?

Quote:
> Thus, I disagree with your statement ""You'll never need full/parallel case
> pragmas, at least in one case:  one-hot logic. And even then you could get
> around. So don't use them!"

I can't see why the IEEE Verilog RTL synthesis Draft collides with my
statement. But that should be easy to clarify:
you, or anyone else here, should then be able to give an example of a piece
of code, where you really need a parallel_case!

Lars
--
Address:  University of Mannheim; D7, 3-4; 68159 Mannheim, Germany
Tel:      +(49) 621 181-2716, Fax: -2713

Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/



Mon, 19 Jul 2004 18:34:51 GMT  
 difference between case and if statements
<should then be able to give an example of a piece
of code, where you really need a parallel_case!>
Ok here is a sample code tested on SYnplicity's Synplify Pro, along with
results:
module muxnew4 (out, a, b, c, d, select);
output out;
input a, b, c, d;
input [3:0] select;
reg out;

begin
        casez (select) /* synthesis parallel_case */
                4'b???1: out = a;
                4'b??1?: out = b;
                4'b?1??: out = c;
                4'b1???: out = d;
                default: out = 'bx;
        endcase
end
endmodule // muxnew4
// Logic resources:  2 LCs of 576 ( 0%) when parallel case directive is ON
// Logic resources:  3 LCs of 576 ( 0%) when parallel case directive is
commented OFF
//    With the parallel case commented off, I get the equivalent of IF with
priority.
// Target was Altera Flex10K .

module muxnew4if (out, a, b, c, d, select);
output out;
input a, b, c, d;
input [3:0] select;
reg out;

        if (select[0]) out = a;
        else if (select[1]) out = b;
        else if (select[2])      out = c;
        else if (select[3])      out = d;
        else out = 'bx;
endmodule // muxnew4if
// Logic resources:  3 LCs of 576 ( 0%)

Bottom line, you need the parallel case directive to infer no priority.
----------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  

Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

Quote:

> Note:The parallel_case attribute is commonly used to remove priority encoders
> from the gate-level implementation of an RTL case statement.Unfortunately,the
> RTL case statement may still simulate like a priority encoder,causing a
> mismatch between pre-synthesis and post-synthesis simulations.

I find this description somehow confusing. They are saying you get mismatches,
which is true. That should be a reason to not use it, right?

Quote:
> Thus, I disagree with your statement ""You'll never need full/parallel case
> pragmas, at least in one case:  one-hot logic. And even then you could get
> around. So don't use them!"

I can't see why the IEEE Verilog RTL synthesis Draft collides with my
statement. But that should be easy to clarify:
you, or anyone else here, should then be able to give an example of a piece
of code, where you really need a parallel_case!


Tue, 20 Jul 2004 01:54:53 GMT  
 difference between case and if statements

Quote:

>         casez (select) /* synthesis parallel_case */
>                 4'b???1: out = a;
>                 4'b??1?: out = b;
>                 4'b?1??: out = c;
>                 4'b1???: out = d;
>                 default: out = 'bx;
>         endcase

Ok, this is a one-hot coded mux. The only place where you need the parallel_case.

Quote:
> // Logic resources:  2 LCs of 576 ( 0%) when parallel case directive is ON
> // Logic resources:  3 LCs of 576 ( 0%) when parallel case directive is OFF
> Bottom line, you need the parallel case directive to infer no priority.

Not exactly.
You could also code the one-hot input explicitly as:
  4'b0001
  4'b0010
  4'b0100
  4'b1000

Why would you do that? Because you have no more a simulation/synthesis
mismatch. And to prevent that i would spend a few gates more. Of course,
if you have a state machine with 30 or more states and you'd like to use
a one-hot coding: use the parallel_case. But a few gates more are no problem
today, in most cases.
But it's a big problem, when one of your customers comes along:
"Hey, i found the reason for the malfunctioning chips. We forgot that not all input
conditions to module x are one-hot. I wonder why the RTL simulations haven't
stumbled about it ..."

Well, just my opinion...
Lars
--
Address:  University of Mannheim; D7, 3-4; 68159 Mannheim, Germany
Tel:      +(49) 621 181-2716, Fax: -2713

Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/



Sat, 24 Jul 2004 04:19:11 GMT  
 difference between case and if statements
The whol;e purse of that code was to demonstrate the parallel case directive.  
As I recalled, I was challanged to show the need for such a directive.
With the directive, I got a paralle case, with no priority.  Without the
parallel case directive I got the equivalent to an "if" statement for the
"case", and got priority.  

About the code,  I am missing the point you are making about the one-hot and
synthesis / simulation mismatch.    The code used in this demo effectively gave
priority to the LSB if it were a 1, else to the next bit to the left.  The ?
are truly don't care, and have nothing to do with one-hot.  Sorry, but I am
missing the point that you are making.   In my previous email, I write the
equivalent of the case code with the "if" statement.  
I also see not simualton/synthesis mismatch.  
-------------------------------------------------------------------------
Ben Cohen     Publisher, Trainer, Consultant    (310) 721-4830  

Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ",  2001 isbn  0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------

Quote:

>>         casez (select) /* synthesis parallel_case */
>>                 4'b???1: out = a;
>>                 4'b??1?: out = b;
>>                 4'b?1??: out = c;
>>                 4'b1???: out = d;
>>                 default: out = 'bx;
>>         endcase

>Ok, this is a one-hot coded mux. The only place where you need the
>parallel_case.

>> // Logic resources:  2 LCs of 576 ( 0%) when parallel case directive is ON
>> // Logic resources:  3 LCs of 576 ( 0%) when parallel case directive is OFF
>> Bottom line, you need the parallel case directive to infer no priority.

>Not exactly.
>You could also code the one-hot input explicitly as:
>  4'b0001
>  4'b0010
>  4'b0100
>  4'b1000

>Why would you do that? Because you have no more a simulation/synthesis
>mismatch. And to prevent that i would spend a few gates more. Of course,
>if you have a state machine with 30 or more states and you'd like to use
>a one-hot coding: use the parallel_case. But a few gates more are no problem
>today, in most cases.
>But it's a big problem, when one of your customers comes along:
>"Hey, i found the reason for the malfunctioning chips. We forgot that not all
>input
>conditions to module x are one-hot. I wonder why the RTL simulations haven't
>stumbled about it ..."



Sat, 24 Jul 2004 13:17:15 GMT  
 difference between case and if statements


Quote:
>About the code,

[inserted from previous post]

Quote:
>         casez (select) /* synthesis parallel_case */
>                 4'b???1: out = a;
>                 4'b??1?: out = b;
>                 4'b?1??: out = c;
>                 4'b1???: out = d;
>                 default: out = 'bx;
>         endcase
>  I am missing the point you are making about the one-hot and
>synthesis / simulation mismatch.    The code used in this demo effectively gave
>priority to the LSB if it were a 1, else to the next bit to the left.  The ?
>are truly don't care, and have nothing to do with one-hot.  Sorry, but I am
>missing the point that you are making.   In my previous email, I write the
>equivalent of the case code with the "if" statement.  
>I also see not simualton/synthesis mismatch.  

Sorry, I'm with Lars on this (except that you sometimes need
parallel logic for *speed* rather than area).  

Ben Cohen's one-hot en-  (de-? re-?) coder
is one of the two classical Verilog formulations;  the other is
given at the end of this post, just for fun.

The parallel_case defective, oops sorry directive, forces synthesis
to create parallel logic instead of priority logic.  So far so good.
How does the parallel logic work?  Many possible solutions,
but something like this is OK (in principle only - it's
incorrect if a,b,c,d,out are wider than 1 bit):

out = (a & select[0]) | (b & select[1]) | ... etc.

So, if more than one bit is set in select[], synthesis gives
the logical OR of more than one of the data signals.

Other implementations of the parallel logic will give different
wrong answers if more than one bit of select[] is set.

But simulation will give a data signal corresponding to the
least significant '1' bit, since simulation ignores parallel_case
and implements this, as required by the Verilog case semantics:

out = select[0] ? a
                : select[1] ? b
                            : select[2] ? c... etc.

It never happens in VHDL of course, since all VHDL case statements
are parallel from the definition of the language.  Far less in
VHDL can you do this...

 casez (1'b1)  /* synthesis parallel_case */
  select[0]: out = a;
  select[1]: out = b;
  select[2]: out = c;
  select[3]: out = d;
  default:   out = 'bx;
 endcase

May all your cases be full and parallel :-)
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom

Fax: +44 1425 471573                             Web: http://www.doulos.com

                   **********************************
                   **  Developing design know-how  **
                   **********************************

This e-mail and any  attachments are  confidential and Doulos Ltd. reserves
all rights of privilege in  respect thereof. It is intended for the  use of
the addressee only. If you are not the intended  recipient please delete it
from  your  system, any  use, disclosure, or copying  of this  document  is
unauthorised. The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Sat, 24 Jul 2004 16:49:03 GMT  
 difference between case and if statements

Quote:

>    casez (select) /* synthesis parallel_case */
>            4'b???1: out = a;
>            4'b??1?: out = b;
>            4'b?1??: out = c;
>            4'b1???: out = d;
>            default: out = 'bx;
>    endcase

You could also try:

     case (1'b1)
       select[0]: out = a;
       select[1]: out = b;
       select[2]: out = c;
       select[3]: out = d;
       default:   out = 'bx;
     endcase

I seem to remember that DC generated a simple mux for this (but that
might have been in conjunction with a parallel_case directive). Don't
know about synplicity though.

Petter
--
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com



Sun, 25 Jul 2004 00:03:40 GMT  
 
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