Synthesizing the initial statement 
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 Synthesizing the initial statement

I tried posting a reply to the original, but you'd set the newsgroups
line to your own e-mail address!

> I am trying to write synthesizable code for the following:
> reg A,B,C,D;
> wire NA,reset,clk;
> initial
>   begin
>     A = 0;
>     B = 0;
>     C = 1;
>     D = 1;
>   end

 ( other code deleted - NOTE: coding in a reset is no different to any other
   signal, there's nothing magic about the word "reset")

>     ... However, it is possible that there will
> be no external RESET and I need to start with a particular value
> (0 or 1) in the registers A,B,C,D.
> My first question is : how can I change my code such that the above
> code can be synthesized ? (Assuming an initial statement is not
> supported by the Verilog synthesizer..)
> Can this be done without an external RESET
> input to a module which would contain code as above?
> Secondly, approx. how many of the Verilog Synthesis Tools can handle
> pullup and pulldown sources?

If I can answer a question with a question, how would you design it yourself
in real gates (or components)? If you are using a technology that does not
guarantee reset state and you want to avoid frightening analogue components
(resistors, capacitors & diodes!), then you will have to use some form of
self-triggering monostable. In order to synthesize this, you simply need
to describe the monostable in rtl code (I think that, for current
synthesis technology, it will have to be sychronous), which is pretty
straightforward & I'll leave it as an exercise for the reader.

If you have a technology with a guaranteed power-up condition, then simply
define your variables so that your desired default condition is (eg) all
zero's & the gate level library should take care of it. If you do really
want a c-r reset circuit, then define it outside the realm of your synthesis
(this could be outside the circuit, OR in a "dont_touch" block) & treat it
as an external circuit. Finally, some (disreputable) synthesizers do offer
"automatic" reset generation. This is generally where the tool assumes
that you forgot to put an external reset & happily invents one for you.
Personally I think this is a dreadful idea!

Perhaps one day synthesizers will produce what you ask for, but don't hold
your breath! First they must learn: 1, asynchronous circuits & loops; 2,
analogue circuits; 3. power supply sequencing. So I suspect it's a long way

As an afterthought: I may have misinterpreted what you were looking for.
It is quite feasable to design "self-resetting" state machines, which
will be guaranteed to go from any initial state to the default state in a
given number of cycles, as long as their control inputs are idle. This is
old science and may be done by explicitly assigning all values of the state
variable (more efficient) of using a "case..default..next_state = idle" type
of construct (quick & lazy). The caveat for this method is that it will
simulate nicely in HDL, but will die horribly in gate level unless you
put some initial state in (because of the x & ~x problem!).

Hope this helps,


< not speaking for ACRI, this post started from an undefined state! >

Tue, 07 Jan 1997 16:12:03 GMT  
 [ 1 post ] 

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