$setup and $hold 
Author Message
 $setup and $hold

I have a couple of questions on the $setup and $hold Verilog system tasks
which I hope someone can help me with.

1.  Conditioned events

  Suppose I have 3 signals: data, clk, and enable.  I wish to declare
  setup and hold timing checks as shown below:

  $setup( data, posedge clk &&& enable, 10 );
  $hold ( data, posedge clk &&& enable, 5 );

  At exactly what time(s) does enable have to be valid (active) for the
  timing check to occur?  
  i.e.:
     a) Will the timing check occur if it is valid at the refrence event,
        but not for the entire interval from 10 time units before to 5
        time units after the refrence event?

     b) Will the timing check occur if enable changes its value in the
        same time unit as the refrence event (posedge clk)?

     example:
        wire enable = ((STATE === `T2) && READY) ? 1 : 0;


                if ((STATE === `T2) && READY)
                    STATE = `T1;

     (note that enable will go inactive in the same time unit as
      the event posedge clk.)

2.  Timing violation reporting

  Is there a way to turn off Verilog's automatic reporting but still
  have it change the value in the notifier register?  For example,
  I would prefer to report the error in a much more informative format:

  i.e. instead of:

  "cpu.v", 33: Timing violation in TOP.CPU
  $setup( DATA:125, (posedge CLK):133.6, Tsetup:10.3);

  I would prefer:

  Timing violation on signal DATA at 133.6 ns in module TOP.CPU.
  DATA failed to meet the setup time of 10.3 ns (Tsetup) relative to CLK.
  Actual seperation was 8.6 ns.

  a)  Is there a way to print out the module that found the violation?
      i.e. TOP.CPU

  b)  Is there a way to get at the time of the last event on any given
      signal?  i.e. something like DATA.time so that the report could
      use something like:
        $display("Actual seperation was %t.", $time - DATA.time);

Thanks for your help,

Jonathan
--
-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-

Graduate Student Research Assistant
Advanced Computer Architecture Lab



Sat, 10 Feb 1996 01:57:28 GMT  
 $setup and $hold

: I have a couple of questions on the $setup and $hold Verilog system tasks
: which I hope someone can help me with.

: 1.  Conditioned events

:   Suppose I have 3 signals: data, clk, and enable.  I wish to declare
:   setup and hold timing checks as shown below:

:   $setup( data, posedge clk &&& enable, 10 );
:   $hold ( data, posedge clk &&& enable, 5 );

:   At exactly what time(s) does enable have to be valid (active) for the
:   timing check to occur?  

I am not an expert - but by reading between the lines of the Verilog-XL
manual, it states that the &&& is an operator that conditions the event. By
'definition' an event is an instantaneous thing, it exists AT a particular
time FOR zero time. If this is indeed the case then the value of enable only
matters at the instant the event 'posedge clock' occurs.

:   i.e.:
:      a) Will the timing check occur if it is valid at the refrence event,
:         but not for the entire interval from 10 time units before to 5
:         time units after the refrence event?

I believe so.

:      b) Will the timing check occur if enable changes its value in the
:         same time unit as the refrence event (posedge clk)?

Here you are getting into a sticky situation. I suspect that the answer is
'maybe'. Unless there is a special mechanism for things that occur in specify
blocks, this boils down to the question of 'if two events are scheduled to
occur in the same time tick, which occurs first?' The answer to this is that
it is undetermined. In one implementation of Verilog (remember verilog is
an open language) one may well observe that one always seems to occur before
he other, but in another implementation of verilog this will not hold. In
general it is safe to make the assumption that there is no such thing as
'order' for two simultaneous events.

:      example:
:       wire enable = ((STATE === `T2) && READY) ? 1 : 0;


:               if ((STATE === `T2) && READY)
:                   STATE = `T1;

:      (note that enable will go inactive in the same time unit as
:       the event posedge clk.)

This code is a bit dangerous. As is, the answer to the question is 'who knows'.
But this kind of code may cause 'incorrect' behaviour for reasons other than
the setup/hold check. All events that occur within the same time tick (at the
same time) may occur in any order. Consider this.


        d2 = d1;


        d1 = d;

One might think that this will create code where d2 will follow d two clock
cycles later. In fact, it may be 2 or it may be 1. If the two simultaneous
events occur in the order they are written then it will indeed be 2. If on
the other hand they occur in reverse order then on one tick d1 will be
assigned the value d, and THEN d2 will be assigned the value d1, which has
already changed. The way to avoid this is to use blocking or non-blocking
(delayed) procedural assignments. Changing your original code to read


                if ((STATE === `T2) && READY)
                    STATE = #1 `T1;

or


                if ((STATE === `T2) && READY)
                    STATE <= #1 `T1;

will avoid both the setup/hold question as well as problems with order
dependant code.

: 2.  Timing violation reporting

:   Is there a way to turn off Verilog's automatic reporting but still
:   have it change the value in the notifier register?  For example,
:   I would prefer to report the error in a much more informative format:

I was sure that there was a way to turn of verilogs automatic reporting
mechanism, but I couldn't remember what it was... I tried to find it but
failed. Someone else??? As for the more informative message, you can
certainly put it in


        $display(etc...);

:   i.e. instead of:

:   "cpu.v", 33: Timing violation in TOP.CPU
:   $setup( DATA:125, (posedge CLK):133.6, Tsetup:10.3);

:   I would prefer:

:   Timing violation on signal DATA at 133.6 ns in module TOP.CPU.
:   DATA failed to meet the setup time of 10.3 ns (Tsetup) relative to CLK.
:   Actual seperation was 8.6 ns.

:   a)  Is there a way to print out the module that found the violation?
:       i.e. TOP.CPU

Yes. In a $display command if you put %m in the format specifier then verilog
will fill it in with the instance name.

:   b)  Is there a way to get at the time of the last event on any given
:       signal?  i.e. something like DATA.time so that the report could
:       use something like:
:       $display("Actual seperation was %t.", $time - DATA.time);

Not that simple. If you REALLY want it, you can do

real DATAtime;


        DATAtime=$realtime;

(or you can do it with integers if you are satisfied with integer times...)


notify,


begin
   $display("Timing violation on signal data at %t in module %m.",$realtime);
   $display("data failed to meet the setup time of %t (Tsetup) rel to CLK",
        Tsetup);
   $display("Actual separation was %t",$realtime-DATAtime);
end

with Tsetup being a parameter used both here and in the timing check.
I don't believe that there is any automated way of doing this for all
timing checks...

:      

: Thanks for your help,

: Jonathan
: --
: -~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-

: Graduate Student Research Assistant
: Advanced Computer Architecture Lab

--

Avrum Warshawsky

Hewlett-Packard (Canada) LTD.



Sat, 10 Feb 1996 07:43:44 GMT  
 $setup and $hold

: I have a couple of questions on the $setup and $hold Verilog system tasks
: which I hope someone can help me with.

: 1.  Conditioned events

:   Suppose I have 3 signals: data, clk, and enable.  I wish to declare
:   setup and hold timing checks as shown below:

:   $setup( data, posedge clk &&& enable, 10 );
:   $hold ( data, posedge clk &&& enable, 5 );

:   At exactly what time(s) does enable have to be valid (active) for the
:   timing check to occur?  
:   i.e.:
:      a) Will the timing check occur if it is valid at the refrence event,
:         but not for the entire interval from 10 time units before to 5
:         time units after the refrence event?

:      b) Will the timing check occur if enable changes its value in the
:         same time unit as the refrence event (posedge clk)?

:      example:
:       wire enable = ((STATE === `T2) && READY) ? 1 : 0;


:               if ((STATE === `T2) && READY)
:                   STATE = `T1;

:      (note that enable will go inactive in the same time unit as
:       the event posedge clk.)

: 2.  Timing violation reporting

:   Is there a way to turn off Verilog's automatic reporting but still
:   have it change the value in the notifier register?  For example,
:   I would prefer to report the error in a much more informative format:

:   i.e. instead of:

:   "cpu.v", 33: Timing violation in TOP.CPU
:   $setup( DATA:125, (posedge CLK):133.6, Tsetup:10.3);

:   I would prefer:

:   Timing violation on signal DATA at 133.6 ns in module TOP.CPU.
:   DATA failed to meet the setup time of 10.3 ns (Tsetup) relative to CLK.
:   Actual seperation was 8.6 ns.

:   a)  Is there a way to print out the module that found the violation?
:       i.e. TOP.CPU

:   b)  Is there a way to get at the time of the last event on any given
:       signal?  i.e. something like DATA.time so that the report could
:       use something like:
:       $display("Actual seperation was %t.", $time - DATA.time);
:      

: Thanks for your help,

: Jonathan
: --
: -~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-~-

: Graduate Student Research Assistant
: Advanced Computer Architecture Lab

To disable the default warning, use the $disable_warnings system task
described in the v1.6a release notes.

I haven't tried it, but judging by its description it does what you want.
_______________
Oren Rubinstein

Hewlett-Packard (Canada) Ltd.

20 Lexington Rd.                         TEL (519) 883-3067
Waterloo, Ontario N2J-3Z3                FAX (519) 886-8620
CANADA

Disclaimer: the above opinions are my own; I do not speak for HP.



Sat, 10 Feb 1996 23:29:20 GMT  
 $setup and $hold
This may have been an error in your posting (rather than in your simulation),
but the parameters for $setup and $hold don't quite match. They are:

        $setup ( data_event, reference_event, ...)

        $hold  ( reference_event, data_event, ...)



Sun, 11 Feb 1996 02:08:05 GMT  
 
 [ 4 post ] 

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