gray code counter in asyn FIFO design 
Author Message
 gray code counter in asyn FIFO design

Hi,

I have been designing Asynchronous FIFO using Gray Code Counter to generate
the Full and Empty Flags. So far it has been sucessful. But recently,
someone asked me why gray code is needed and if I can provide some failure
cases on paper for illustration when gray code is not used. I was stuck.

Can someone give me a concrete example of a failure case when gray code is
not used? Not just some general ideas like one bit change at a time or
pessimistic flag status (I can find all this from the web). Thanks.

PK



Sat, 14 Aug 2004 15:25:34 GMT  
 gray code counter in asyn FIFO design

Quote:

> Hi,

> I have been designing Asynchronous FIFO using Gray Code Counter to generate
> the Full and Empty Flags. So far it has been sucessful. But recently,
> someone asked me why gray code is needed and if I can provide some failure
> cases on paper for illustration when gray code is not used. I was stuck.

> Can someone give me a concrete example of a failure case when gray code is
> not used? Not just some general ideas like one bit change at a time or
> pessimistic flag status (I can find all this from the web). Thanks.

> PK

Hi.
I highly recommand on the paper :

http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk_rev...

I quote from this paper :

"Any FIFO pointer that must be synchronized into a different clock
domain should not be implemented as a binary counter.
One characteristic of binary counters is that half of all sequential
binary incrementing operations
require that two or more counter bits must change. Trying to
synchronize a binary counter into a
new clock domain is more problematic than trying to synchronize
multiple control signals into a
new clock domain. If a simple 4-bit binary counter changes from
address 7 (binary 0111) to
address 8 (binary 1000), all four counter bits will change at the same
time. If a synchronizing
clock edge comes in the middle of this transition, it is possible that
any 4-bit binary pattern could
be sampled and synchronized into the new clock domain as shown in
Figure 15."

To see the figure, you are adviced to downlaod the paper ...
Bye,
Nahum.



Sat, 14 Aug 2004 20:35:50 GMT  
 
 [ 2 post ] 

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