Memory leak in VCS 
Author Message
 Memory leak in VCS

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Hello folks:

This posting is for the people that use or have used
the Chronologic Verilog compiler VCS.
While we were running a compiled verilog simulation which seemed
to work fine, we noticed that the memory allocated to the simv
process (simv is the default executable name that VCS gives
to the compiled Verilog) was constantly expanding. In the end,
the process died because of a malloc error (no more memory
available). The simulation results are correct, time advances
fine and the same verilog code executes in constant memory
when we use plain old Cadence Verilog. Simulation results
are the same in both cases.

I am trying to isolate as small a test case as possible and
send it to the Viewlogic people. I will also post it here.

Did anybody of you see any similar behavior from VCS at any
point?

I must mention that VCS is in general an excellent product
which has enabled us to run verilog jobs so large that it
was absolutely impossible to run them before because of
memory and speed limitations.

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Tue, 22 Apr 1997 12:51:58 GMT  
 
 [ 1 post ] 

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