Verilog netlists from Edge schematics 
Author Message
 Verilog netlists from Edge schematics

Hi,

Can anyone tell me if it is possible to extract Verilog netlists from
Cadence Edge which can cope with contending drive strengths ?

eg A weak feedback inverter....

The problem that I have is that the extracted netlist does not contain
any information about the differing drive strengths and as a result I
get unknowns propagating. Transistor sizing properties such as w and l
don't seem to make any difference. Is there any property I can add to
specify different strengths ?

Thanks a lot.

--
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+ Shiv Sikand                                     +
+ AMULET Research, Department of Computer Science +
+ The University, Oxford Road, Manchester M13 9PL +

+          ! I speak only for myself !            +
+   ---> Power savers do it asynchronously <---   +
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Wed, 24 May 1995 04:17:54 GMT  
 Verilog netlists from Edge schematics

Quote:

>Can anyone tell me if it is possible to extract Verilog netlists from
>Cadence Edge which can cope with contending drive strengths ?

>eg A weak feedback inverter....

Give the inverter the following properties:

   High_Strength = weak1
   Low_Strength = weak0

pull, strong, etc. can be substituted for weak as desired.  These properties
are not well documented but there is a *brief* discussion of them in ch12
of the Design Analysis manual.

--

Design Automation Engineer     |  1-214-450-8115
Dallas Semiconductor           |

--
--

Design Automation Engineer       214-450-8115
Dallas Semiconductor



Tue, 30 May 1995 03:57:38 GMT  
 
 [ 2 post ] 

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