Which is easier to learn VHDL or Verilog 
Author Message
 Which is easier to learn VHDL or Verilog

Hi, all. I want to say before that I'm new to this world. I plan to go the
univerity in electrical engineering (after my college), and in the second
year, they will learn us VHDL. I taught it's was the only language in the
world to "code devices". Than I found that others lnaguage exist like
Verilog. I want to learn one of this language before they teach it.

So I ask you which one is : 1) Easier to learn, 2) More use in the industry
(which one I will benefist the most), 3) What is the advantage and
inconvenient of both language?

Thanks you in advance!

P.S: If this can help in your answer, I already have a strong programming
background in C/C++, so programming it's no obscur to me.



Sun, 01 Sep 2002 03:00:00 GMT  
 Which is easier to learn VHDL or Verilog
It doesn't matter,

Where VHDL is over-architected, and sometimes has you in contortions to get
things done, Verilog is under-architected and allows you to point at your feet
more often than needed.

It took me 5 days to learn the other kowing one (VHDL->Verilog / EU -> US)  and
someone else I know made the opposite transition (Verilog->VHDL /US-> EU) with
similar ease.

I.e. don't worry, the differences are small, don't get too skill/tool centric,
it's a dead-end career killer.

My $0.02

Tom
Works with ASICs
Tandem



Sun, 01 Sep 2002 03:00:00 GMT  
 Which is easier to learn VHDL or Verilog

Opinion: verilog is easier to learn and more prevalent
in ASIC design ... (at least in the US).

Principal Engineer
Avici Systems, Inc.



Mon, 02 Sep 2002 03:00:00 GMT  
 Which is easier to learn VHDL or Verilog
You could have a look at this Verilog FAQ pages:
http://www.angelfire.com/in/rajesh52/verilog.html
Under section "Technical Papers" you will find some Verilog-VHDL
comparisons.

Lars
--
Address:  University of Mannheim; B6, 26; 68159 Mannheim, Germany
Tel:      +(49) 621 181-2716, Fax: -2713

Homepage: http://mufasa.informatik.uni-mannheim.de/lsra/persons/lars/



Mon, 02 Sep 2002 03:00:00 GMT  
 Which is easier to learn VHDL or Verilog

Quote:

> So I ask you which one is : 1) Easier to learn, 2) More use in the industry
> (which one I will benefist the most), 3) What is the advantage and
> inconvenient of both language?

> Thanks you in advance!

> P.S: If this can help in your answer, I already have a strong programming
> background in C/C++, so programming it's no obscur to me.

Well,

        ask yourself what you want. Here are some questions.

Do you like fighting against trouble? Do you prefer programming
Windows with MFC?
Learn VHDL and spent a lot of nights collecting packages with
convertion functions from one type to another.

Do you like to talk with every gate you generate? Do you like to check
tons of lines in a netlist?
Learn Verilog and drive into real hardware stuff.

Do you want to become a professor with many students{*filter*} on your
lips? Do you want earn money with your consulting firm?
Learn VHDL and offer your solution for problems your costumer doesn't
have before.

Do you want to work under the Sun of California?
Learn Verilog.

Ups, you want to become a real Asic Designer? You want to understand
fantasic designs? You want to get results in a short time? You want to
describe your imaginations on a abstract level? You want to build good
testbenches?
Sorry, there's no HDL of your choice. Learn both VHDL *and* Verilog.

Hope this helps
hsank.



Mon, 02 Sep 2002 03:00:00 GMT  
 Which is easier to learn VHDL or Verilog

<splendidly cynical take on VHDL vs Verilog>

Quote:
> Hope this helps

It certainly does.  Saved for future reference (and for showing
to my classes, if you don't mind!).

Thanks for the smile.
Jonathan Bromley



Mon, 02 Sep 2002 03:00:00 GMT  
 Which is easier to learn VHDL or Verilog
Hi
According to "ME" (just to make sure I don't trigger any comp.lang.hdl* wars),
for a person who has programmed in C, Verilog is a better choice; because
Verilog has the same feel as C, while VHDL is based on ADA (I think so).
But apart from that as the others have mentioned, the change from one to the
other shouldn't be too difficult.

have fun learning (and unlearning) HDLs
cheers
Yeshwant

Quote:

> Hi, all. I want to say before that I'm new to this world. I plan to go the
> univerity in electrical engineering (after my college), and in the second
> year, they will learn us VHDL. I taught it's was the only language in the
> world to "code devices". Than I found that others lnaguage exist like
> Verilog. I want to learn one of this language before they teach it.

> So I ask you which one is : 1) Easier to learn, 2) More use in the industry
> (which one I will benefist the most), 3) What is the advantage and
> inconvenient of both language?

> Thanks you in advance!

> P.S: If this can help in your answer, I already have a strong programming
> background in C/C++, so programming it's no obscur to me.



Mon, 02 Sep 2002 03:00:00 GMT  
 Which is easier to learn VHDL or Verilog


Quote:
> Hi, all. I want to say before that I'm new to this world. I plan to go the
> univerity in electrical engineering (after my college), and in the second
> year, they will learn us VHDL. I taught it's was the only language in the
> world to "code devices". Than I found that others lnaguage exist like
> Verilog. I want to learn one of this language before they teach it.

> So I ask you which one is :

> 1) Easier to learn,

Not a very important question.  You're question number 2 is probably the
best one.  Both aren't too bad to learn.  I personally think the underlying
"model" of VHDL is cleaner which will make it easier to understand for a
beginner.  For example, in VHDL, a SIGNAL is a wire, plain and simple.  In
Verilog, what is the difference between a WIRE and a REG?  I'm not talking
about in terms of the language, I'm talking about in terms of the hardware.  
If you describe a "combinational" signal with a continuous assignment
statement, that signal is a WIRE.  If you describe the exact same
combinational circuit in a different way (with an IF or a CASE for
example), now all of a sudden the signal becomes a REG.  This kind of thing
confuses beginners, but you get used to it so don't worry (note: getting
used to it does not mean the same thing as it making sense).

Quote:
> 2) More use in the industry
> (which one I will benefist the most),

Good question.  Impossible to answer.  It depends on many many things such
as where you work, who you work for and random chance.  You're email looks
like Canada so if you plan to live your life in Canada, you should find out
which language is most prevalent there (or if its mixed).  The fact that
the ciriculum of your University does not offer Verilog may be a hint.  I
think Europe is predominately VHDL.  The US is definitely mixed, though
pockets like Silicon Valley are predominately Verilog.  Here at IBM we are
very mixed and it varies not only from team to team, but project to
project.  This is because we work with teams from all over the world, some
of which are other IBMers in another location and some of which are joint
development projects with other companies.  *It really pays to be well
versed in both*.  This way you will be marketable at more companies and
more locations.  For this reason alone, I would suggest that you spend your
time now to learn Verilog because you will be learning VHDL later in the
university.

Quote:
> 3) What is the advantage and
> inconvenient of both language?

Again, this question is much less relevant than your number 2 (which I said
was impossible to answer, so why am I posting?? :-) )  They are both good.  
They are both bad.  They both have advantages.  They both have
disadvantages.  I think a better language can be designed that takes the
good from both of them and corrects or leaves out the bad.  The important
thing is that you will probably need both and if you don't need both, the
choice of which one to use will likely not be your choice -- at least not
until you are the lead designer and the customer of your chip doesn't care
about the design language.

Quote:

> P.S: If this can help in your answer, I already have a strong programming
> background in C/C++, so programming it's no obscur to me.

Before learning either VHDL or Verilog, I would strongly advise you to get
a good background in "digital logic design".  VHDL and Verilog "look"
somewhat like programming languages but they are not programming languages
at all.  Trying to design logic like you would program is disastrous.  I've
seen programmer type people try to do it with some very bad results --
"look, the HDL has FOR loops -- Cool!" (I'm not saying FOR loops aren't
appropriate in some instances, but you *really* have to know where).  In
fact, I would say that if you don't know logic design, your programming
background may hurt you rather than help you.  Chips are not little
computers running software coded in VHDL or Verilog.  You need to be able
to visualize the hardware circuits and state machines you are trying to
implement before ever coding a line of HDL.

By the way, how are you planning to learn VHDL or Verilog?  You really
won't learn much just by reading a book.  So you will need to find some
tools that will actually allow you to work with the language.  What you can
get may influence which language you wish to persue for now.  You
definitely need a compiler/simulator to try out your designs.  You will
need a synthesizer to synthesize your designs into gates.  A simulator will
simulate any legal code, but only a subset of the constructs are
synthesizeable.  Without a synthesizer you won't know if your code can be
realized on a real FPGA or ASIC and meet some timing goal.  So you should
first find out what kind of tools you can get access to, either for free or
on your budget.  FPGA tools are probably the best place to start since ASIC
tools are generally much more expensive and require much more setup of the
libraries and such.  I don't know of any free tools, but that doesn't mean
they don't exist.  Good luck.  I hope you found some of this useful.

--
Rich Iachetta

I do not speak for IBM.



Mon, 02 Sep 2002 03:00:00 GMT  
 Which is easier to learn VHDL or Verilog

Quote:

> For example, in VHDL, a SIGNAL is a wire, plain and simple.

Not if you infer flip-flops from it ... :-)

Quote:
> In Verilog, what is the difference between a WIRE and a REG?  I'm not talking
> about in terms of the language, I'm talking about in terms of the hardware.

Mm, neither in Verilog nor in VHDL there is a straightworward
interpretation of wire/reg & signal/variable in terms of hardware.
Trying to find one is what confuses people more than accepting
there isn't one. It really depends on how the things are used
in HDL code.

Having said that, the Verilog wire is perhaps the exception here.

Regards, Jan

--
Jan Decaluwe           Easics              
Design Manager         System-on-Chip design services  
+32-16-395 600         Interleuvenlaan 86, B-3001 Leuven, Belgium



Tue, 03 Sep 2002 03:00:00 GMT  
 Which is easier to learn VHDL or Verilog

Quote:
> > For example, in VHDL, a SIGNAL is a wire, plain and simple.

> Not if you infer flip-flops from it ... :-)

I see what you're saying but it makes sense to me to think of all VHDL
SIGNALs as wires.  At the top of the architecture a bunch of SIGNALs are
defined which are the wires that connect up the logic (and other
instantiated blocks) described below.  The logic below may synthesize into
gates, flip-flops, latches, etc. but the input and output of that logic and
instanitated blocks connect up to these wires.  If I decide that one of my
continuous assignment statements is getting too complicated and I want to
write the same function with IF,THEN,ELSE, I don't have to go renaming the
output of that function from SIGNAL to something else just to code the same
logic like I do in Verilog (renaming the WIRE to a REG).  REG is an ultra
confusing term because its name seems to imply some kind of register (flip-
flop or latch) but that's not at all the case.

No comment about VHDL variables as I don't use them in synthesizable logic.

--
Rich Iachetta

I do not speak for IBM.



Tue, 03 Sep 2002 03:00:00 GMT  
 Which is easier to learn VHDL or Verilog
I am not an expert but  I feel that the hardest and most confusing thing to
understand about logical design is the difference between sequential and
concurrent statements and the concept of sensitivity lists.   In this sense
Verilog is clearer and more logical than VHDL.  What I really don't like is the
"begin end" syntax of both of them.  I
think it should be changed to the bracelets in C.  Let me know if you have
different opinions.


Tue, 12 Nov 2002 03:00:00 GMT  
 Which is easier to learn VHDL or Verilog

A lot of C programmers who try to write the VHDL or Verilog code have
the same complaints as yours. But hey, "begin end"  are here to stay,
your goal is to learn the basic syntaxs and constructs, not to waste
time to modify it.

================================================================


Quote:
> I am not an expert but  I feel that the hardest and most confusing
thing to
> understand about logical design is the difference between sequential
and
> concurrent statements and the concept of sensitivity lists.   In this
sense
> Verilog is clearer and more logical than VHDL.  What I really don't
like is the
> "begin end" syntax of both of them.  I
> think it should be changed to the bracelets in C.  Let me know if you
have
> different opinions.

Sent via Deja.com http://www.deja.com/
Before you buy.


Wed, 13 Nov 2002 03:00:00 GMT  
 Which is easier to learn VHDL or Verilog
....

Quote:
>  What I really don't like is the
> "begin end" syntax of both of them.  I
> think it should be changed to the bracelets in C.  

actually I did some experiments a few years back with my Verilog compiler.
Putting in C-style { } compounds as well as begin end ones is pretty
easy (from memory there was one trivial gramatical ambiguity that would
have been pretty easy to resolve).

The main downside I see is that {} has taken a new meaning in verilog
and having it mean different things in different places could easily be
confusing, esp. to new users.

OTOH being someone who sometimes prototypes algorithms in C and has
to later convert them to verilog I know it's a pain being so close to
C, but not quite enough ....

        Paul Campbell



Wed, 13 Nov 2002 03:00:00 GMT  
 Which is easier to learn VHDL or Verilog

If you know "C", Verilog is easier to learn.
If you know "Ada", VHDL is easier. :-)
Raja Gosula

  rgosula.vcf
< 1K Download


Wed, 20 Nov 2002 03:00:00 GMT  
 
 [ 14 post ] 

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