Parallel or Sequential That is The Question! 
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 Parallel or Sequential That is The Question!

This question is directed to all Verilog users.  Suppose I have the following code:

module XX(clock)
input clock


if (condition) begin      ]
   ..                     ]=== Condition #1
   end                    ]

if (condition) begin      ]
   ..                     ]=== Condition #2
   end                    ]

endmodule

==================

Question:

Will the two conditions run in parallel in the simulator (Verilog-XL)?  Will the two conditions be placed in to run in parallel during synthesis to generate a parallel running schematic?  Or will the execution be sequential?  If this is the case, how do I get them to run in parallel???  

Thanks in advance for your attention,

Phil

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Sun, 12 Jan 1997 23:29:15 GMT  
 Parallel or Sequential That is The Question!

Quote:

>This question is directed to all Verilog users.  Suppose I have the following code:

>module XX(clock)
>input clock


>if (condition) begin      ]
>   ..                     ]=== Condition #1
>   end                    ]

>if (condition) begin      ]
>   ..                     ]=== Condition #2
>   end                    ]

>endmodule

>==================

>Question:

>Will the two conditions run in parallel in the simulator (Verilog-XL)?  Will the two conditions be placed in to run in parallel during synthesis to generate a parallel running schematic?  Or will the execution be sequential?  If this is the case, how do I get them to run in parallel???  

If you want to run them sequentially, place them in a begin-end block.
If you want them to run in parallel, place them in a fork-join block.
When run in parallel, the actual order of simulation will be ambiguous
in any given time unit.  (From my experience condition 1 will execute
first in the time unit).  In either case, the above syntax will not compile
as the two if blocks must either be encased in a begin-end block or a
fork-join block, or be of the type if-elseif.

Jonathan

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Graduate Student Research Assistant
Advanced Computer Architecture Lab
157 ATL Building
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The University of Michigan
Ann Arbor, MI  48109-2110

ph. (313) 764-2138
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Mon, 13 Jan 1997 02:31:58 GMT  
 Parallel or Sequential That is The Question!

Quote:

>This question is directed to all Verilog users.  Suppose I have the following code:

>module XX(clock)
>input clock


>if (condition) begin      ]
>   ..                     ]=== Condition #1
>   end                    ]

>if (condition) begin      ]
>   ..                     ]=== Condition #2
>   end                    ]

>endmodule

>==================

>Question:

>Will the two conditions run in parallel in the simulator (Verilog-XL)?  Will the two conditions be placed in to run in parallel during synthesis to generate a parallel running schematic?  Or will the execution be sequential?  If this is the case, how do I get them to run in parallel???  

Yes, they will simulate in "parallel" wrt simulation time. Verilog XL
will execute them sequentially, but since you dont have any timing delays
shown, they will execute in the same time slot (but in sequential

blocks, since any timing delays in the body of the first if block will
affect the second if block:


begin

  if (condition) begin
        a = 1;
        #10 a = 0;
  end

  if (condition) begin
        b = 1;
        #15 b = 0;
  end

end

In this example b wont be set to 1 until time 10. Note you left out a
begin/end pair for the body of the always block.

Safer Parallel version:


begin

  if (condition) begin
        a = 1;
        #10 a = 0;
  end

end


begin

  if (condition) begin
        b = 1;
        #15 b = 0;
  end

end

In this example, b is set to 1 at the negedge of clock.

And yes, with Synopsys the two "if" statements can be made into parallel gate
level circuits. (Note, synopsys ignores the #delay construct, so you
can't use it for synthesis purposes..) Again, it is safer to use two
always blocks if you really want the two "ifs" to be independent.

--
Gord Wait       S-MOS Systems Vancouver Design Centre
                (B.C. Canada eh!)



Tue, 14 Jan 1997 01:02:06 GMT  
 
 [ 3 post ] 

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