synthesis related question 
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 synthesis related question

Quote:

> Hello there,

> I have a question related to Verilog and Synthesys.

> In the following statement:

> wire [3:0] d ;
> wire [2:0] a, b ;
> wire c_in ;

> assign d = 4'b0 + a + b + c_in ;

> Is the synthesizer going to infer adders for zeros as well? How many adders
> are going to be there?

The synthesizer will probably infer an adder for the zeros and then
optimize it out during logic optimization.  You should end up with 3
adders.

--
Mark Lancaster



Mon, 04 Jun 2001 03:00:00 GMT  
 synthesis related question

Quote:

>In the following statement:

>wire [3:0] d ;
>wire [2:0] a, b ;
>wire c_in ;

>assign d = 4'b0 + a + b + c_in ;

>Is the synthesizer going to infer adders for zeros as well? How many adders
>are going to be there?

>regards,
>mohsin

Mohsin, depending on some Synopsys variables that effect how Verilog is
initially mapped (which most people don't ever mess with), your initial
mapping should include the 4'b0 but it'll be very quickly optimized out
with even the lowest level compile -- thus you'll have 2 adders.  Wait
a minute!  You're messing with bus-widths!  Whoa!  I'm not sure how
that'll be handled and it might very likely depend on the exact rev of
Synopsys you're using how it handles that "c_in".  To be safe, you may
want to concatenate 3'b0 to "c_in" to make it the same bit-width as
"a" and "b".
                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

============================================================================
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 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!


     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."



Mon, 04 Jun 2001 03:00:00 GMT  
 synthesis related question
Actually, design compiler is smart enough to infer a carry-in to
the LSB when a one-bit signal is added to two multi-bit signals.
This is very useful!  I don't know what the 4'd0 will do in this
code, but if it were merely a + b + cin, DC would infer a single
DW01_add.  If the 4'd0 is there simply to force the output expression
width to 4 bits, don't bother.  DC will infer the 4 bit output
properly without it, since wire d is four bits wide.

        Paul Dormitzer
        Broadband Access Systems

Quote:


> >In the following statement:

> >wire [3:0] d ;
> >wire [2:0] a, b ;
> >wire c_in ;

> >assign d = 4'b0 + a + b + c_in ;

> >Is the synthesizer going to infer adders for zeros as well? How many adders
> >are going to be there?

> >regards,
> >mohsin

> Mohsin, depending on some Synopsys variables that effect how Verilog is
> initially mapped (which most people don't ever mess with), your initial
> mapping should include the 4'b0 but it'll be very quickly optimized out
> with even the lowest level compile -- thus you'll have 2 adders.  Wait
> a minute!  You're messing with bus-widths!  Whoa!  I'm not sure how
> that'll be handled and it might very likely depend on the exact rev of
> Synopsys you're using how it handles that "c_in".  To be safe, you may
> want to concatenate 3'b0 to "c_in" to make it the same bit-width as
> "a" and "b".



Tue, 05 Jun 2001 03:00:00 GMT  
 synthesis related question

Quote:
>Actually, design compiler is smart enough to infer a carry-in to
>the LSB when a one-bit signal is added to two multi-bit signals.
>This is very useful!

I know this is right with most revs of DC, but I'm not sure if it's always
been (or always will be) true because he's adding three numbers of two
different bit widths.  There's no artificial intelligence that I know of
with DC that sees "c_in" and deduces it's a carry in bit -- instead it
just treats it intially as doing a single bit add to a multi-bit number
and the best beastie it can find that matches that function is an adder
with a carry in.  Hmmm....   After saying that I realize that by doing
this, it is effectively recognizing the carry in bit...   Hmmmm...   On
second thought, you're right, absolutely right on this one.  Time to get
back to the Christmas grog...  3^)

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

============================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 6000+ other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!


     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."



Tue, 05 Jun 2001 03:00:00 GMT  
 synthesis related question

Quote:




> > > Hello there,

> > > I have a question related to Verilog and Synthesys.

> > > In the following statement:

> > > wire [3:0] d ;
> > > wire [2:0] a, b ;
> > > wire c_in ;

> > > assign d = 4'b0 + a + b + c_in ;

> > > Is the synthesizer going to infer adders for zeros as well? How many adders
> > > are going to be there?

> > The synthesizer will probably infer an adder for the zeros and then
> > optimize it out during logic optimization.  You should end up with 3
> > adders.

> Why 3 adders? Shouldnt it be just one adder.

I should have said a single three bit wide adder.

--

Motorola WMSD  M/S: CH275   phone: (602)814-4920            
1300 N. Alma School Rd.     fax:   (602)814-3107
Chandler, AZ 85224



Fri, 08 Jun 2001 03:00:00 GMT  
 
 [ 7 post ] 

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