Q: Verilog VS VHDL/VITAL for Gate Level Simulation
Quote:
> > Any benchmarks or other considerations re: choosing Verilog or VITAL for
> > gate level simulation ?
> From what I hear VITAL model take up a lot more memory and take longer to
> simulate than their verilog equivalent and that's when the foundry provides
> them.
> regards,
> Padraig
You know, from what I've heard, VITAL models can alter your design
during the backannotation phase, introducing bugs that weren't there
in the first place.
And I've also heard that the memory that they allocate can never be
deallocated, so eventually you have to buy new memory chips or trash
your computer.
And just the other day, I heard that Elvis has been hired to write the
next generation of VITAL packages! And who would want to use
libraries based on packages written by a dead rock star?
Yep - you read it right here on comp.lang.verilog, so it must be true!
Martin.
