HDL code to multiply a clock
Author Message
HDL code to multiply a clock

Dear All,
Will anybody please share to me a simple logic to multiply a clock( in
vhdl or verilog). Say 1 Mhz to 2 Mhz. How to keep the multiplied clock's
duty cycle to perfect or near perfect 50 %.
Regards

Sun, 10 Feb 2002 03:00:00 GMT
HDL code to multiply a clock

Quote:

> Dear All,
>   Will anybody please share to me a simple logic to multiply a clock( in
> vhdl or verilog). Say 1 Mhz to 2 Mhz. How to keep the multiplied clock's
> duty cycle to perfect or near perfect 50 %.

Create two flip-flops.  Clock one using the posedge of your clock and
the other using the negedge.  EXOR their Q outputs.  This creates a
50% duty cycle multiply by 2.

Mark

Sun, 10 Feb 2002 03:00:00 GMT
HDL code to multiply a clock

Quote:

> > Dear All,
> >   Will anybody please share to me a simple logic to multiply a clock( in
> > vhdl or verilog). Say 1 Mhz to 2 Mhz. How to keep the multiplied clock's
> > duty cycle to perfect or near perfect 50 %.

> Create two flip-flops.  Clock one using the posedge of your clock and
> the other using the negedge.  EXOR their Q outputs.  This creates a
> 50% duty cycle multiply by 2.

Sorry,
Mark

Sun, 10 Feb 2002 03:00:00 GMT
HDL code to multiply a clock

Quote:

> Dear All,
>   Will anybody please share to me a simple logic to multiply a clock( in
> vhdl or verilog). Say 1 Mhz to 2 Mhz. How to keep the multiplied clock's
> duty cycle to perfect or near perfect 50 %.
> Thanks a lot in advance.
> Regards

try this, might work

reg CLK2;

CLK2 <= 1'b1;

if (CLK2 == 1)
CLK2 <= #delay 1'b0;
//delay can be varied depending on duty cycle will be 500ns in case of 1MhZ
and 50%duty cycle

anup

Mon, 11 Feb 2002 03:00:00 GMT
HDL code to multiply a clock

Quote:

> Dear All,
>   Will anybody please share to me a simple logic to multiply a clock( in
> vhdl or verilog). Say 1 Mhz to 2 Mhz. How to keep the multiplied clock's
> duty cycle to perfect or near perfect 50 %.
> Thanks a lot in advance.
> Regards

Why do you use 1MHz for the master clock ?
Implement your design with a 2 MHz master clock  and don't get such problem
!   :-)

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Mon, 11 Feb 2002 03:00:00 GMT
HDL code to multiply a clock

Quote:

> > Dear All,
> >   Will anybody please share to me a simple logic to multiply a
clock( in
> > vhdl or verilog). Say 1 Mhz to 2 Mhz. How to keep the multiplied
clock's
> > duty cycle to perfect or near perfect 50 %.
> reg CLK2;

>                CLK2 <= 1'b1;

> if (CLK2 == 1)
>     CLK2 <= #delay 1'b0;

Very interesting problem.  Looks easier than it is.
After looking at it for a while (after coffee!)
you realize: you *can't* do this in synchronous
logic.  You need something *analog* like a #delay
(which an RTL synthesizer won't accept) or a
PLL (the common approach).  No way to guarantee
50% duty cycle.

-----------
There are no ifdefs in hardware.

Sent via Deja.com http://www.deja.com/
Share what you know. Learn what you don't.

Sat, 02 Mar 2002 03:00:00 GMT
HDL code to multiply a clock

Of course, if your are just trying to model a frequency multiplier it is
quite possible.  You can use the \$time task along with some math
(divide) to get the appropriate #delay function for a new clock.  You
'll need to set the time scale to be finer than the period you playing
with. Keeping the new clock aligned is a bit more trickey though, but
can be done.

One of the things you should never count on is that the input signal has
a 50 % duty cycle.

integer newtime, oldtime;
parameter ratio = 2;
initial new_clk = 1'b0;

begin
newtime = \$time;
half_period = ((oldtime - newtime) / ratio) / 2);
oldtime = newtime;
end

always #half_period new_clk = ~new_clk;

Nonetheless this is almost entirely an analog problem to get a piece of
REAL hardware to do this.  If you know what technology you are using,
you could design multitap digital counter with a phase locking mechanism
to do the job (the dital counter needs to run MUCH faster than the clock
you are trying to generate.)

Quote:

> > > Dear All,
> > >   Will anybody please share to me a simple logic to multiply a
> clock( in
> > > vhdl or verilog). Say 1 Mhz to 2 Mhz. How to keep the multiplied
> clock's
> > > duty cycle to perfect or near perfect 50 %.

> > reg CLK2;

> >                CLK2 <= 1'b1;

> > if (CLK2 == 1)
> >     CLK2 <= #delay 1'b0;

> Very interesting problem.  Looks easier than it is.
> After looking at it for a while (after coffee!)
> you realize: you *can't* do this in synchronous
> logic.  You need something *analog* like a #delay
> (which an RTL synthesizer won't accept) or a
> PLL (the common approach).  No way to guarantee
> 50% duty cycle.

> -----------
> There are no ifdefs in hardware.

> Sent via Deja.com http://www.deja.com/
> Share what you know. Learn what you don't.

Wed, 20 Mar 2002 03:00:00 GMT

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