Hi,
I have all the inputs to a full adder. How to write verilog code so that
after synthesis
synopsys uses its own designware fulladder. now i am doing as follows:

assign {cout,sum}=A+B+cin;

But after synthesis it uses two adders from designware library. I want cin
to goto "real" Cin.

Thanks
Azhar

Set the variable hdlin_use_cin to ture...

Matt

: Hi,
: I have all the inputs to a full adder. How to write verilog code so that
: after synthesis
: synopsys uses its own designware fulladder. now i am doing as follows:
:
: assign {cout,sum}=A+B+cin;
:
: But after synthesis it uses two adders from designware library. I want cin
: to goto "real" Cin.
:
: Thanks
: Azhar
:
:
:
:
:

Would you please elaborate it. I am new to this.
Thanks,
Azhar

In your .synopsys_dc.setup file add this line:

hdlin_use_cin = true

Matt

: Would you please elaborate it. I am new to this.
: Thanks,
: Azhar
:


: > Set the variable hdlin_use_cin to ture...
: >
: > Matt
: >

: > : Hi,
: > : I have all the inputs to a full adder. How to write verilog code so that
: > : after synthesis
: > : synopsys uses its own designware fulladder. now i am doing as follows:
: > :
: > : assign {cout,sum}=A+B+cin;
: > :
: > : But after synthesis it uses two adders from designware library. I want
: cin
: > : to goto "real" Cin.
: > :
: > : Thanks
: > : Azhar
: > :
: > :
: > :
: > :
: > :
:
: