Mismatch between timing violations and vcd files using SDF. 
Author Message
 Mismatch between timing violations and vcd files using SDF.

I am running simulations of a chip including sdf backannotation. I have
experienced cases where a timing violation is reported at a flip-flop, but
where, if I examine the waveforms (generated from the vcd file) or display
the times the relevent signals change using $monitor, no such violation
should occur. The timing of the CLK / D changes reported by the violation
statement, and those seen in the $monitor / vcd results are not the same.
I am guessing that somehow the vcd values refer to the time the signal
changed at the driver, and that the time taken to cross the wire is not
properly included. Is this the case ? Is there any work-around ?

---
Gavin  



Mon, 16 Sep 1996 18:08:48 GMT  
 Mismatch between timing violations and vcd files using SDF.

Quote:

>I am running simulations of a chip including sdf backannotation. I have
>experienced cases where a timing violation is reported at a flip-flop, but
>where, if I examine the waveforms (generated from the vcd file) or display
>the times the relevent signals change using $monitor, no such violation
>should occur. The timing of the CLK / D changes reported by the violation
>statement, and those seen in the $monitor / vcd results are not the same.
>I am guessing that somehow the vcd values refer to the time the signal
>changed at the driver, and that the time taken to cross the wire is not
>properly included. Is this the case ? Is there any work-around ?

My guess is that the SDF file being annotated contains 'INTERCONNECT'
delays.  This delay cannot be observed by probing the wire you would
expect it to be applied to.  It is annotated as a MIPD.  Probe after
the buffer on the input in the receiving cell and you should see what
you expect.  It is begin simulated correctly (most likely!), just
difficult to observe.
--Robert Brashears



Fri, 20 Sep 1996 23:50:10 GMT  
 
 [ 2 post ] 

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